什么是ARM安全模式分区检查 [英] What is partition checker in ARM Secure Mode

问题描述

根据这个链接
的http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0333h/Chdfjdgi.html

在

系统引导顺序
...

程序分区检查分配提供给非安全操作系统的物理内存。

什么是分区检查？难道其中有寄存器的一个子系统，什么是它的编程模型？

解决方案

  

什么是分区检查？

有CPU的<青霉> TrustZone的的规范之外。然而，在螺母外壳它分区或划分存储器空间分成不同的允许的访问。如果访问是不允许的，它抛出一个的外部总线错误的

  

难道其中有寄存器的一个子系统，什么是它的编程模型？

典型地，它是一串寄存器。它也许多寄存器文件。例如，一个APB（外围总线），AHB（较早的ARM总线）和一个新的AXI（的TrustZone知道总线）可以全部在一个系统present。甚至有可能出现多个APB总线等。

在同一页面，

  

的TrustZone存储器管理的原理是将物理存储器分成安全和非安全区域。

应该补充的分区的在大师为安全的和的非安全的也很重要。在分区的是ARM CPU的TrustZone规范之外;它是总线架构的一部分。它是由一个总线控制器/结构来实现这一点。总线控制器既大师的（的CPU，DMA外设等），的奴的（存储设备，注册接口等）连接。

分区的在ARM TrustZone的文档的上下文是有点模糊的，因为它是由每个SOC和总线控制器（和等级）实施的细节。如上所述，它的分区或分存储空间分成不同的允许访问。这就像导师，而使用传统的ARM（ AMABA ）AHB总线的用户访问。该AXI接口增加了一个 NS 位。

下面是可能的组合为一的总线控制器的支持。

  |阅读|写
------------- + -------- + -------
普通用户|是/否|是/否
普通|是/否|是/否
安全用户|是/否|是/否
安全超|是/否|是/否
 

的 SCR NS 位将动态确定总线访问NS位是否设置。这是一个的的TrustZone 的区别。对于的超级的和的用户的，有一个传统的 HPROT 位。同时，每个主的将断言写/读〜信号（可能极性不同，但我们的软件而不是硬件）。

一个DMA主机（以太网，USB等），也可发送请求到总线。通常，这些设置和在启动时锁定。如果你的安全的世界使用以太网，那么它可能是一个安全的DMA主机访问安全存储器。以太网芯片还通常具有的从的注册接口。必须标明（或分区）作为的安全的。如果的正常的全球访问的以太网的寄存器文件，然后一个总线错误被抛出。一个供应商也可能使DMA外设动态设置 NS 位根据命令结构。该 CAAM 是一个加密驱动程序，可设置工作描述同时处理的正常的和的安全的访问，作为一个DMA主控其中同时做两件事的一个例子。

一个CPU（说的Cor​​tex-M4或Cortex-R），也可能是全球范围内的安全的或的正常的。只有在Cortex-A与系列（和ARMv6的）充分的的TrustZone 的将动态切换的 NS 的位允许CPU既安全和正常的，这取决于上下文。

从外设也许分区。例如，SDRAM的第一个10MB可能正常和安全的读取和写入的跨世界的通信。然后接下来的54MB，也许只是正常读取正常的世界/写。然后读取的最后64MB /写安全为安全的世界。通常情况下，注册外围设备接口是一个全或无设置。

这是一个MMU的范围之外的一切，只用物理地址处理。如果SOC开机后锁定他们，这是任何人都不可能改变的映射。如果安全的世界code是的只读的，它可能更难以工程师的利用。

通常情况下，所有APB总线是一个AHB总线，它可以连接到AXI总线主像一棵树上的层次感。该AXI总线是一个的Cortex-A的默认。每个总线将有奴隶和主人的列表，并支持各种的是的和的没有的配置，这可能上面的列表的一个子集;也就是说，它可能不关心的读/写或超级/用户的或其他一些排列。这将是为每个ARM系统的不同。在一些情况下，一个供应商可能甚至不支持它。在这种情况下，也许更加困难，使系统的安全或者甚至使用TrustZone的。请参阅：处理ARM TrustZones 的，其中一些公交车问题较少的细节都谈到了

请参阅：的TrustZone与虚拟机管理程序这给一些更多的细节。

As per this link http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0333h/Chdfjdgi.html

under

System boot sequence ...

Program the partition checker to allocate physical memory available to the Non-secure OS.

What is the partition checker? Is it a subsystem which has registers, what is its programming model ?

解决方案

What is the partition checker?

It is outside of the TrustZone specification for the CPU. However, in a nut shell it partitions or divided memory spaces into different permitted accesses. If the access is not permitted, it throws an external BUS error.

Is it a subsystem which has registers, what is its programming model?

Typically, it is a bunch of registers. It maybe multiple register files. For instance, an APB (peripheral bus), AHB (older ARM bus) and a new AXI (TrustZone aware bus) may all be present in one system. There may even be multiple APB buses, etc.

From the same page,

The principle of TrustZone memory management is to partition the physical memory into Secure and Non-secure regions.

It should be added that partitioning the masters as secure and non-secure is also important. The partitioning is outside the ARM CPU TrustZone specification; it is part of the BUS architecture. It is up to a bus controller/structure to implement this. The bus controller has both masters (CPUs, DMA peripherals, etc) and slaves (memory devices, register interfaces, etc) connected.

Partitioning in the context of the ARM TrustZone document is a little nebulous as it is up to each SOC and the bus controllers (and hierarchy) to implement the details. As above, it partitions or divided memory spaces into different permitted accesses. This is just like supervisor versus user access with traditional ARM (AMABA) AHB buses. The AXI interface adds an NS bit.

Here are possible combinations for a bus controller to support.

             |  Read  | Write 
-------------+--------+-------
Normal User  | yes/no | yes/no
Normal Super | yes/no | yes/no
Secure User  | yes/no | yes/no 
Secure Super | yes/no | yes/no

The SCR NS bit will dynamically determine whether the 'NS' bit is set on bus accesses. This is a TrustZone difference. For the super and user, there is a traditional HPROT bit. As well, each master will assert a WRITE/~READ signal (maybe the polarity is different, but we are software not hardware).

A DMA master (Ethernet, USB, etc) may also send out requests to a BUS. Typically, these are setup and locked at boot time. If your secure world uses the Ethernet, then it is probably a secure DMA master to access secure memory. The Ethernet chip also typically has a slave register interface. It must be marked (or partitioned) as secure. If the normal world accesses the ethernet register file, then an BUS error is thrown. A vendor may also make DMA peripherals that dynamically set the NS bit depending on the command structure. The CAAM is a crypto driver that can setup job descriptions to handle both normal and secure access, as an example of a DMA master which does both.

A CPU (say Cortex-M4 or Cortex-R) may also be globally secure or normal. Only the Cortex-A series (and ARMv6) with full TrustZone will dynamically toggle the NS bit allowing the CPU to be both secure and normal, depending on context.

Slave peripherals maybe partitioned. For example, the first 10MB of SDRAM maybe both normal and secure read and write for inter-world communication. Then next 54MB, maybe normal only read/write for the normal world. Then a final 64MB of read/write secure for the secure world. Typically, register interfaces for peripherals are an all or none setup.

These are all outside of the scope of an MMU and deal only with physical addresses. If the SOC locks them after boot, it is impossible for anyone to change the mapping. If the secure world code is read-only, it maybe more difficult to engineer an exploit.

Typically, all APB buses are layered on an AHB bus, which connects to an AXI main bus like a tree. The AXI bus is the default for a Cortex-A. Each BUS will have a list of slaves and masters and will support various yes and no configurations, which maybe a subset of the list above; Ie, it may not care about read/write or super/user or some other permutations. It will be different for each ARM system. In some cases, a vendor may not even support it. In this case, it maybe more difficult to make the system secure or even use TrustZone. See: Handling ARM TrustZones‌​, where some of the bus issues are touched on in less details.

See: TrustZone versus Hypervisor which gives some more details.

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