什么是ARM的启动过程？ [英] What is the booting process for ARM?

问题描述

据我们所知，对于X86架构：经过我们preSS电源按钮，机器开始在0xFFFFFFF0执行code，然后开始在BIOS中才能做到硬件初始化执行code。 BIOS执行后，用它来引导程序将操作系统映像加载到内存中。最后，OS code开始运行。
对于ARM架构，什么是使用后preSS电源按钮的启动过程？
谢谢！

As we know, for X86 architecture: After we press the power button, machine starts to execute code at 0xFFFFFFF0, then it starts to execute code in BIOS in order to do hardware initialization. After BIOS execution, it use bootloader to load the OS image into memory. At the end, OS code starts to run. For ARM architecture, what is the booting process after use press the power button? Thanks!

推荐答案

目前，也有ARM架构两个异常模型（复位被认为是一种例外）：

Currently, there are two exception models in the ARM architecture (reset is considered a kind of exception):

经典机型，在pre-的Cortex芯片和当前的Cortex-A / R芯片使用。在这里面，在0存储器包含若干异常处理程序：

The classic model, used in pre-Cortex chip and current Cortex-A/R chips. In it, the memory at 0 contains several exception handlers:

 Offset  Handler
 ===============
 00      Reset 
 04      Undefined Instruction
 08      Supervisor Call (SVC)
 0C      Prefetch Abort
 10      Data Abort
 14      (Reserved)
 18      Interrupt (IRQ)
 1C      Fast Interrupt (FIQ)

当异常情况发生时，处理器只是开始执行从一个特定的偏移量，所以通常这表包含单指令分支在code完整的处理程序进一步。一个典型的经典量表看起来像下面这样：

When the exception happens, the processor just starts execution from a specific offset, so usually this table contains single-instruction branches to the complete handlers further in the code. A typical classic vector table looks like following:

00000000   LDR   PC, =Reset
00000004   LDR   PC, =Undef
00000008   LDR   PC, =SVC
0000000C   LDR   PC, =PrefAbort
00000010   LDR   PC, =DataAbort
00000014   NOP
00000018   LDR   PC, =IRQ
0000001C   LDR   PC, =FIQ

在运行时，量表可以搬迁到0xFFFF0000地址，这往往是作为一个紧密耦合内存范围最快的异常处理实现。然而，上电复位通常开始于00000000（但在一些芯片可以由处理器销被设置为0xFFFF0000地址）。

At runtime, the vector table can be relocated to 0xFFFF0000, which is often implemented as a tightly-coupled memory range for the fastest exception handling. However, the power-on reset usually begins at 0x00000000 (but in some chips can be set to 0xFFFF0000 by a processor pin).

新的微控制器模型在芯片的Cortex-M的行中使用。还有，在0矢量表实际上是向量（指针），而不是指令的表。第一项包含SP寄存器的启动值，第二是复位矢量。这允许直接在C ++编写的复位处理程序，因为处理器设置堆栈。此外，该表可在运行时重新定位。用于Cortex-M典型的量表是这样开始的：

The new microcontroller model is used in the Cortex-M line of chips. There, the vector table at 0 is actually a table of vectors (pointers), not instructions. The first entry contains the start-up value for the SP register, the second is the reset vector. This allows writing the reset handler directly in C, since the processor sets up the stack. Again, the table can be relocated at runtime. The typical vector table for Cortex-M begins like this:

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     MemManage_Handler         ; MPU Fault Handler
                DCD     BusFault_Handler          ; Bus Fault Handler
                DCD     UsageFault_Handler        ; Usage Fault Handler
                [...more vectors...]

请注意，在当今复杂的芯片，如OMAP3或苹果的A4被执行code的第一块通常不是用户code，但片上引导ROM。它可能会检查各种条件，以确定从哪里加载用户code和是否在所有加载它（例如，它可能需要一个有效的数字签名）。在这种情况下，用户code可能具有以符合不同的启动约定。

Note that in the modern complex chips such as OMAP3 or Apple's A4 the first piece of code which is executed is usually not user code but the on-chip Boot ROM. It might check various conditions to determine where to load the user code from and whether to load it at all (e.g. it could require a valid digital signature). In such cases, the user code might have to conform to different start-up conventions.

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