SV 或 UVM 中的正则表达式 [英] Regex in SV or UVM
问题描述
在 Systemverilog/UVM 中使用正则表达式需要调用哪些函数?
What functions do I need to call to use Regular Expressions in Systemverilog/UVM?
注意:我不是在问如何使用正则表达式,只是在问方法名.
Note: I'm not asking how to use regular expressions, just method names.
推荐答案
首先,如果您想使用正则表达式,您需要确保您使用的是与其 DPI 代码一起编译的 UVM 库(即UVM_NO_DPI
定义未设置).
First, if you want to use regular expression, you'll need to make sure you're using a UVM library compiled together with its DPI code (i.e. the UVM_NO_DPI
define isn't set).
您要使用的方法位于dpi/uvm_regex.svh
.主要函数是 uvm_re_match(...)
,它将正则表达式和要匹配的字符串作为参数.这基本上是对 regex.h
库中的 regexec(...)
C 函数的封装.它会在匹配时返回 0
.
The methods you want to use are located in dpi/uvm_regex.svh
. The main function is uvm_re_match(...)
, which takes as an argument a regular expression and the string to match against. This is basically a wrapper around the regexec(...)
C function found in the regex.h
library. It will return 0
on a match.
您可能想要使用的另一个函数是 uvm_glob_to_re(...)
,它可以将 glob 表达式(您在 Linux shell 中获得的那种)转换为真正的正则表达式.
Another function you might want to use is uvm_glob_to_re(...)
which can convert from a glob expression (the kind you get in a Linux shell) to a true regular expression.
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