从测试平台访问 uvm_config_db 的最佳方式? [英] Best way to access the uvm_config_db from the testbench?

问题描述

我想在我的顶级测试平台中创建一个时钟，其周期可以通过测试进行控制.我所做的是将时间段设置到 uvm_config_db 中并将其返回到测试台中.我必须输入 #1 以确保构建阶段完成，否则 get 返回错误值:

I want to create a clock in my top level testbench whose period can be controlled from the test. What I did was set the period into the uvm_config_db and get it back in the testbench. I had to put in a #1 to make sure that the build phase was finished, otherwise the get returned the wrong value:

module testbench_top;
  int clk_period;

  bit clk = 0;

  initial begin
    #1;    
    void'(uvm_config_db #(int) ::get(null, "uvm_test_top.env", "clk_period", clk_period));
    // Create clk
    forever begin
      #(clk_period/2) clk = !clk;
    end
  end

我对#1 感到恼火.有没有更好的方法来检查配置是否已设置?我可以以某种方式阻止直到 start_of_simulation_phase 吗?

I am annoyed by the #1. Is there a better way to check that the config has been set? Can I somehow block until start_of_simulation_phase?

推荐答案

我发现它隐藏在类参考中:您可以使用 _ph 访问每个阶段的全局单例版本.然后我可以使用 wait_for_state 函数阻塞直到模拟阶段开始.模拟，它似乎工作:

I found it buried in the class reference: You can access the global singleton versions of each phase with <phase name>_ph. Then I can use the wait_for_state function to block until the start of the start of simulation phase. Simulated and it seems to work:

module testbench_top;
  int clk_period;

  bit clk = 0;

  initial begin
    start_of_simulation_ph.wait_for_state(UVM_PHASE_STARTED);    
    if(!uvm_config_db #(int) ::get(null, "uvm_test_top.env", "clk_period", clk_period))
      `uvm_fatal("CONFIG", "clk_period not set");
    // Create clk
    forever begin
      #(clk_period/2) clk = !clk;
    end
  end

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