从循环变量创建一个 int 参数 [英] Create a int parameter from a loop variable

问题描述

我正在尝试使用与此类似的代码来工作:

I am trying to get a code similar to this to work:

module testModule #(    parameter LEN = 4,
                        parameter logic [0:0] OPTION = 1'b0 )
(
    input               Clk,
    input     [LEN-1:0] DataIn,
    input     [LEN-1:0] Condition,
    output    [LEN-1:0] DataOut_1,
    output    [LEN-1:0] DataOut_2
);

    // CODE 1
    always_ff @(posedge Clk) begin
        for (int i = 0; i < LEN; i++) begin
            if (OPTION == 1'b0) begin
                if (Condition[0]) begin
                    DataOut_1[i] <= DataIn[i];
                end else begin
                    DataOut_1[i] <= 1'b0;
                end
            end else begin
                if (Condition[i]) begin
                    DataOut_1[i] <= DataIn[i];
                end else begin
                    DataOut_1[i] <= 1'b0;
                end
            end
        end
    end

    // CODE 2
    always_ff @(posedge Clk) begin
        for (int i = 0; i < LEN; i++) begin
            int select = (OPTION == 1'b0) ? 0 : i;
            if (Condition[select]) begin
                DataOut_2[i] <= DataIn[i];
            end else begin
                DataOut_2[i] <= 1'b0;
            end
        end
    end

endmodule

OPTION 可以是 0 或 1.

OPTION can be either 0 of 1.

我希望 CODE 1 和 2 做同样的事情，我正在尝试简化 CODE 1.

I would like CODE 1 and 2 to do the same thing, and I am trying to simplify CODE 1.

DataOut_1 和 DataOut_2 返回相同的值，但在 CODE 2 中出现以下错误int select = (OPTION == 1'b0) ?0 : i;

DataOut_1 and DataOut_2 return the same value, but I get the following errors in CODE 2 in line int select = (OPTION == 1'b0) ? 0 : i;

带有初始化器的局部静态变量需要'static'关键字

静态变量初始化器中的自动变量非法

我不确定是否有办法做到这一点

And I am not sure if there is a way to do it

推荐答案

您可以使用三元和按位运算符代替 for 循环来简化 CODE 1:

You can simplify CODE 1 by using a ternary and bitwise operator instead of the for loop:

module testModule #(    parameter LEN = 4,
                        parameter logic [0:0] OPTION = 1'b0 )
(
    input                Clk,
    input      [LEN-1:0] DataIn,
    input      [LEN-1:0] Condition,
    output reg [LEN-1:0] DataOut_1
);
    always_ff @(posedge Clk) begin
        if (OPTION == 1'b0) begin
            DataOut_1 <= (Condition[0]) ? DataIn : '0;
        end else begin
            DataOut_1 <= DataIn & Condition;
        end
    end
endmodule

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