Verilog:在赋值的左侧必须具有可变数据类型 [英] Verilog: on left-hand side of assignment must have a variable data type
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问题描述
我在组合分配时遇到问题.我不明白为什么我不能使用始终组合结构来设置我的输出变量.当我使用assign时,我没有收到分配错误.
I am having trouble with combination assignment. I do not understand why I cannot use a always combination structure the set my output variables. When I use assign, I do not get the assignment error.
我认为assign和always@(*)都意味着阻塞(组合赋值)
I thought assign and always@(*) both means blocking (combinational assignment)
module control_unit(input wire [31:0] instruction
,output wire RegDst
,output wire ALUSrc
,output wire RegWrite
,output wire MemRead
,output wire MemWrite
,output wire MemToReg
,output wire Branch
);
wire [5:0] opcode;
assign opcode = instruction[31:26];
always@(*) begin
case(opcode)
6'b000000: begin // r-type
RegDst = 1'b1;
ALUSrc = 1'b0;
RegWrite = 1'b1;
MemRead = 1'b0;
MemWrite = 1'b0;
MemToReg = 1'b0;
Branch = 1'b0;
end
.
.
.
default: begin
RegDst = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
MemRead = 1'b0;
MemWrite = 1'b0;
MemToReg = 1'b0;
Branch = 1'b0;
end
endcase
end // end always_comb
endmodule
推荐答案
您不能对 wire
进行程序分配.您必须对 reg
进行程序分配,无论 always
块是描述顺序逻辑还是组合逻辑.使用以下端口声明:
You cannot make a procedural assignment to a wire
. You must make a procedural assignment to a reg
, regardless of whether the always
block describes sequential or combinational logic. Use the following port declarations:
,output reg RegDst
,output reg ALUSrc
,output reg RegWrite
,output reg MemRead
,output reg MemWrite
,output reg MemToReg
,output reg Branch
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