编码 D 触发器的更好方法 [英] better way of coding a D flip-flop

问题描述

最近，我在verilog中看到一些D触发器RTL代码是这样的:

Recently, I had seen some D flip-flop RTL code in verilog like this:

    module d_ff(
            input d,
            input clk,
            input reset,
            input we,
            output q
    );

    always @(posedge clk) begin
            if (~reset) begin
                    q <= 1'b0;
            end
            else if (we) begin
                    q <= d;
            end
            else begin
                    q <= q;
            end
    end
    endmodule

语句 q <= q; 是否必要?

推荐答案

是否有语句 q <= q;有必要吗?

Does the statement q <= q; necessary?

不，它不是，在 ASIC 的情况下，它实际上可能会增加面积和功耗.我不确定现代 FPGA 是如何处理这个问题的.在综合期间，工具将看到该语句并要求在每个正时钟沿更新 q.如果没有最后的 else 子句，工具可以自由地仅在满足给定条件时更新 q.

No it isn't, and in the case of an ASIC it may actually increase area and power consumption. I'm not sure how modern FPGAs handle this. During synthesis the tool will see that statement and require that q be updated on every positive clock edge. Without that final else clause the tool is free to only update q whenever the given conditions are met.

在 ASIC 上，这意味着综合工具可能会插入一个时钟门(如果库有一个)而不是多路复用器.对于单个 DFF，这实际上可能更糟，因为时钟门通常比多路复用器大得多，但如果 q 是 32 位，那么节省的空间可能非常大.现代工具可以自动检测使用共享enable的DFF的数量是否满足某个阈值，然后适当地选择时钟门或mux.

On an ASIC this means the synthesis tool may insert a clock gate(provided the library has one) instead of mux. For a single DFF this may actually be worse since a clock gate typically is much larger than a mux but if q is 32 bits then the savings can be very significant. Modern tools can automatically detect if the number of DFFs using a shared enable meets a certain threshold and then choose a clock gate or mux appropriately.

在这种情况下，该工具需要 3 个多路复用器和额外的路由

In this case the tool needs 3 muxes plus extra routing

always @(posedge CLK or negedge RESET)
  if(~RESET)
    COUNT <= 0;
  else if(INC)
    COUNT <= COUNT + 1;
  else
    COUNT <= COUNT;

此处该工具对所有 DFF 使用单个时钟门

Here the tool uses a single clock gate for all DFFs

always @(posedge CLK or negedge RESET)
  if(~RESET)
    COUNT <= 0;
  else if(INC)
    COUNT <= COUNT + 1;

这里的图片

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