带+1逻辑的4位计数器D触发器 [英] A 4-bit counter D flip flop with + 1 logic

问题描述

我正在尝试通过Verilog实现这个具有+1逻辑的D触发器计数器。但是，我收到了很多关于NET的多个常量驱动程序的错误代码。有人能帮我一把吗？以下是目前为止的代码：

module LAB (clk, clear, Enable, Q);

input clk, clear, Enable;   
    
output[3:0] Q; 
                
reg[3:0] Q;

wire D;

    
assign D = Q;
    
always @ (posedge clk)

begin

if (!clear)

Q <= 1'b0;

else

Q <= D;

end
    
always @ (Enable)

begin

if (Enable == 1)

Q <= D + 1;

else
 
Q <= D;

end 
    
endmodule

以下是我收到的错误代码：

Error (10028): Can't resolve multiple constant drivers for net "Q[3]" at 


LAB.v(17)
Error (10029): Constant driver at LAB.v(9)


Error (10028): Can't resolve multiple constant drivers for net "Q[2]" at LAB.v(17)


Error (10028): Can't resolve multiple constant drivers for net "Q[1]" at LAB.v(22)


Error (10028): Can't resolve multiple constant drivers for net "Q[0]" at LAB.v(22)


Error (12153): Can't elaborate top-level user hierarchy


Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 6 errors, 4 warnings

Error: Peak virtual memory: 4613 megabytes


Error: Processing ended: Sun Apr 19 18:39:09 2020


Error: Elapsed time: 00:00:01


Error: Total CPU time (on all processors): 00:00:00


Error (293001): Quartus II Full Compilation was unsuccessful. 8 errors, 4 
warnings

推荐答案

您有两个不同的always块驱动相同的寄存器Q。您可以将单独的always挡路看作单独的硬件设备。因此，在您的情况下，您有2个触发器输出是连接的。这违反了硬件和合成规则。它还会在模拟期间产生问题。

修复它的唯一方法是创建一个always挡路，它定义了驱动FLUP所需的所有逻辑，如下所示：

always @ (posedge clk or negedge clear) begin
    if (!clear)
        Q <= 1'b0;
    else if (enable)
        Q <= D + 1;
    else 
        Q <= D;
end

我在此不是在评论您的逻辑，只是举个例子，应该可以消除Q的多个驱动程序周围的所有错误。

这篇关于带+1逻辑的4位计数器D触发器的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！