VHDL 程序在 4 位向上计数器中计数到 10 ......? [英] VHDL program to count upto 10 in 4 bit up counter....?

问题描述

     library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_signed.all; 

entity counter is 
  port(CLK, CLR : in  std_logic; 
       output : inout std_logic_vector(3 downto 0)); 
end counter; 
architecture archi of counter is 
  signal tmp: std_logic_vector(3 downto 0); 
  begin 
    process (CLK, CLR)
     variable i: integer:=0;
        begin

           if (CLR='1') then
                tmp <= "0000";
           elsif (clk = '1') then
                for i in 0 to 6 loop
                    tmp <= tmp + 1;
                end loop;
            end if;

数到 7 我在 0 到 10 中为 i 所做的.它没有显示任何错误，但它从 0000 到 1111 计数

to count upto 7 i have done for i in 0 to 10. it is not showing any error but it counts from 0000 to 1111

    end process;
     output <= tmp;

end architecture;

你能建议怎么做吗....抱歉英语语法错误

could you please suggest how to do it....sorry for wrong grammar in english

推荐答案

需要关闭一个时钟沿

因为您的 counter port 中有 clk，我们可以假设您希望计数器与时钟同步计数.

Needs to operate off one clock edge

Because your counter port has clk in it, we can assume you want the counter to count synchronous to the clock.

您在两个时钟边沿都运行

You're operating off of both clock edges

         elsif (clk = '1') then

应该是这样的

         elsif clk'event and clk = '1' then

或

         elsif rising_edge(clk) then

这些示例使用 clk 的上升沿.您不能在 IEEE-1076.6 IEEE VHDL 寄存器标准下合成使用两个时钟边沿的东西传输级 (RTL) 综合.这不是公认的计时方法.

These examples use the rising edge of clk. You can't synthesize something that uses both clock edges under the IEEE-1076.6 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. It's not a recognized clocking method.

假设你希望计数器从 0 到 9 并翻转这个

Under the assumption you want the counter to go from 0 to 9 and rollover this

            for i in 0 to 6 loop
                tmp <= tmp + 1;
            end loop;

应该是这样的

            if tmp = "1001" then         # binary 9
                tmp <= (others => '0');  # equivalent to "0000"
            else
                tmp <= tmp + 1;
            end if;

这模拟了一个同步负载，该负载优先于由外部状态"识别器驱动的增量.通过异步清零，它将模拟一个 74163 4 位计数器，外部 4 输入门识别1001"并产生同步并行负载信号加载0000".

And this emulates a synchronous load that takes priority over increment driven by an external 'state' recognizer. With an asynchronous clear it would emulate an 74163 4 bit counter with an external 4 input gate recognizing "1001" and producing a synchronous parallel load signal loading "0000".

如图所示的循环过程将导致在 "1111" 处产生单个增量和计数器翻转，就像您描述的那样.您可以删除 for ... loop 和 end loop; 语句，它的行为将相同.每个驱动程序的信号只有一个计划未来更新，并且一个进程对于它分配的每个信号只有一个驱动程序.所有循环迭代都发生在同一个 clk 事件中.tmp 直到下一个模拟周期(循环完成后)才会更新，并且它的赋值在所有循环迭代中都是相同的，表达式 tmp + 1.最后一个循环迭代赋值将是实际发生的赋值，并且它赋值的值将相同.

The loop process as shown would result in a single increment and resulting counter rollover at "1111" like you describe. You could remove the for ... loop and end loop; statements and it would behave identically. There's only one schedule future update for a signal for each driver, and a process only has one driver for each signal it assigns. All the loop iterations occur at the same clk event. tmp won't get updated until the next simulation cycle (after the loop is completed) and it's assignment is identical in all loop iterations, the expression tmp + 1. The last loop iterated assignment would be the one that actually occurs and the value it assigns would be identical.

当 counter 是状态驱动的(state ≃ tmp)时，不需要使用循环语句.不需要 i 表示的附加状态.

Using a loop statement isn't necessary when counter is state driven (state ≃ tmp). The additional state represented by i isn't needed.

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