VHDL中的FSM内部计数器 [英] Counter inside FSM in VHDL
问题描述
我的有限状态机有一个小问题，最近我用VHDL编写了
。我试图创建由频率为2 Hz的时钟触发的智能计数器
。
此计数器内置于FSM的一种状态，可通过按DE2板上的
按钮启动。
I have got a small problem with my finite state machine which I have written in VHDL recently. I tried to create "intelligent" counter triggered by clock with frequency 2 Hz. This counter is built in one state of FSM and is started by pushing a button on DE2 board.
首先，整个系统处于IDLE状态状态，如果我按此按钮，状态将
更改为COUNTING，计数器开始增加，并且他当前的
值显示在LED显示屏上。在达到模值之后，状态
COUNTING会回到IDLE，并将计数器设置为零。
Firstly, whole system is in IDLE state and if I push this button, state is changed to COUNTING and counter begin to be incremented and his current value is shown on LED display. After it reach value of modulo, the state COUNTING is left back to IDLE and the counter is set up to zero.
我的问题是计数器没有工作不正常-
的计数值太大。因此，我尝试使用这种结构来解决它：如果
（clk_tick´event和clk_tick = 1）则....，
合成有一些错误：
错误（10822）： Citac_FSM.vhd（57）处的HDL错误：无法在该时钟沿实现
寄存器进行赋值
My problem is that the counter doesn´t work correctly - the counting value was too great. So I tried to solve it with this construction: if (clk_tick´event and clk_tick = 1) then.... , there are some errors by synthesis: Error (10822): HDL error at Citac_FSM.vhd(57): couldn't implement registers for assignments on this clock edge
错误（10821）：Citac_FSM处的HDL错误。 vhd（62）：无法推断
AUTOMAT：flg的注册，因为其行为与任何受支持的寄存器
模型都不匹配
Error (10821): HDL error at Citac_FSM.vhd(62): can't infer register for "AUTOMAT:flg" because its behavior does not match any supported register model
请，有人有解决的办法吗？
用两个（或更多）时钟源编写时钟触发的FSM的正确方法是什么？
Please, does somebody have an idea to solve it? And what is it correct way to write clock triggered FSM with two (or more) clock sources?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
ENTITY Counter_FSM IS
GENERIC (
REGSIZE : integer := 8; -- range of counter
MODULO : natural := 50 -- modulo value
);
PORT (
CLK : IN STD_LOGIC; -- puls 50 MHz
CLK_tick : IN STD_LOGIC; -- puls 2 Hz
RESET : IN STD_LOGIC; -- reset
READY : OUT STD_LOGIC; -- counter is ready to start
START_C : IN STD_LOGIC; -- start of counting
DOUT : OUT STD_LOGIC_VECTOR(REGSIZE - 1 downto 0) --out
);
END Counter_FSM;
ARCHITECTURE Behavior OF Counter_FSM is
type counterState is (IDLE, COUNTING); -- states of FSM
signal currCounterState : counterState; -- current state
signal nextCounterState : counterState; -- next state
signal cnt : std_logic_vector(REGSIZE - 1 downto 0); -- counter
begin
UPDATE: process(RESET, CLK)
begin
if (RESET = '0') then
currCounterState <= IDLE;
elsif (CLK'event and CLK = '1') then
currCounterState <= nextCounterState;
end if;
end process;
COMBI: process (clk_tick, start_c, currCounterState)
variable flg : std_logic := '0';
begin
if (clk_tick'event and clk_tick = '1') then
flg := '1';
end if;
case currCounterState is
when IDLE =>
cnt <= (others => '0'); -- counter value = zero
READY <= '1'; -- we can start
if (start_c = '1') then -- if button is pushed
nextCounterState <= COUNTING; -- go to COUNTING
end if;
when COUNTING =>
READY <= '0';
if (flg = '1') then -- Was there impuls of 2 Hz?
cnt <= cnt + 1; -- yes -> incrementing
flg := '0';
if (cnt = MODULO) then -- if cnt = MODULO
cnt <= (others => '0'); -- then cnt = zero
nextCounterState <= IDLE;
end if;
end if;
when others =>
nextCounterState <= IDLE;
end case;
-- OUTPUT
douT <= cnt;
end process;
end Behavior;
非常感谢。
Mirek
PS：很抱歉，我的英语不太好。
P.S.: I am sorry my English is not so good.
推荐答案
我已经解决了我的问题:-)。我将计数器移到单独的过程中，然后将巫婆信号附加到FSM。因此，它非常好用。
I have already solved my problem :-). I have moved the counter into separate process and then attached witch signals to FSM. So, it works very well.
通过读取按钮，我现在使用两个D触发器对其进行同步。
By reading of button I am using two D flip-flops to synchronize it at the moment.
我必须对VHDL编程的风格进行观察-它与C语言这样的常规编程太不同了：-D
I have to make an observation on style of VHDL programming - it is too different to "normal" programming like C language :-D
美好的一天！
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