VHDL计数器错误（vcom-1576） [英] VHDL Counter Error (vcom-1576)

问题描述

我试图在VHDL中编写一个简单的计数器，但我总是收到此错误：

guys im trying to code a simple counter in VHDL but i always get this error:

Error: C:/Users/usrname/dir1/dir2/dir3/counter.vhd(22): near "rising_edge": (vcom-1576) expecting == or '+' or '-' or '&'.

这是我的代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
port (
EXT_RST : in std_logic;
EXT_CLK : in std_logic;
EXT_LED : out std_logic_vector(7 downto 0)
);
end counter;

architecture fast of counter is

signal count : std_logic_vector(7 downto 0);

begin
process(EXT_CLK, count)
  begin
    if (EXT_RST = '1') then
    count <= "00000000";
    elseif rising_edge(EXT_CLK) then
    count <= count + '1';
    end if;
 end process;
EXT_LED <= count;
end fast;

有人知道为什么我会收到此错误吗？

Has anyone an idea why im getting this error?

推荐答案

除了 elsif Lars Asplund建议在其注释中使用类型转换外，还要使用`count：

Besides the elsif Lars Asplund suggested using in his comment use type conversions for `count:

count <= std_logic_vector(unsigned(count) + 1);

或使用软件包numeric_std_unsigned（仅限VHDL -2008）而不是numeric_std。

or use package numeric_std_unsigned (VHDL -2008 only) instead of numeric_std.

注意 1 而不是'1'类型转换。不需要使用numeric_std_unsigned并带有带有此签名的加号 +的运算符：

Notice the 1 instead of '1' and type conversions. Those aren't needed with numeric_std_unsigned which has a "+" adding operator function with this signature:

[STD_ULOGIC_VECTOR,STD_ULOGIC return STD_ULOGIC_VECTOR]

使用软件包numeric_std，您还可以进行计数以unsigned代替std_logic_vector并转换为LED分配-

Using package numeric_std you can also make count an unsigned instead of std_logic_vector and convert for the LED assignment -

EXT_LED <= std_logic_vector(count);

此外，个计数不需要在进程敏感度列表中：

Also, count doesn't need to be in the process sensitivity list:

process(EXT_CLK)

在该过程中，除时钟沿外，没有使用 count 值的分配。

There are no assignments in the process where the value of count is used except on the clock edge.

使用第一个建议和缩进修改代码（这有助于显示敏感度列表不需要 count ：

Modifying your code with the first suggestion and indenting (which helps show the sensitivity list doesn't need count:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
    port (
        EXT_RST : in std_logic;
        EXT_CLK : in std_logic;
        EXT_LED : out std_logic_vector(7 downto 0)
    );
end counter;

architecture fast of counter is

signal count : std_logic_vector(7 downto 0);

begin
process(EXT_CLK)
  begin
    if (EXT_RST = '1') then
        count <= "00000000";
    elsif rising_edge(EXT_CLK) then
        count <= std_logic_vector(unsigned(count) + 1);
    end if;
 end process;
    EXT_LED <= count;
end fast;

这将进行分析，详细说明并进行模拟。

This analyzes, elaborates and will simulate.

这提示了 EXT_RST 和 EXT_CLK 的问题如果您实际合成设计，则派生。如果它们来自按钮（尤其是时钟），则即使薄膜开关可能会老化并随后反弹，也可能需要进行反跳。

This prompts the question of how EXT_RST and EXT_CLK are derived should you actually synthesize your design. If they are from buttons (particularly the clock), debounce could be necessary even with membrane switches which can age and later bounce.

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