为什么我的 D 触发器不等待时钟的上升沿? [英] Why is my D Flip Flop not waiting for the positive edge of the clock?

问题描述

正如我所知，D 触发器在每个上升沿对其输入值进行采样时钟的.

As I have known, D flipflop samples its input value at every positive edge of the clock.

因此，它将产生 1 个周期的延迟.对吗?

Thus, it will produce a 1 cycle delay. Right?

但是为什么我的 D 触发器不会产生 1 个周期的延迟?

But why does my D flip flop does not produce a 1 cycle delay?

         module flipflop(
             input clk,
             input rstn,
             input [7:0] i_data,
             output reg [7:0] o_data
         );

             always @(posedge clk) begin
                     if (~rstn) begin
                             o_data <= 0;
                     end
                     else begin
                             o_data <= i_data;
                     end
             end
         endmodule

       module test;
           reg clk;
           reg [7:0] i_data;
           reg rstn;
           wire [7:0] o_data;

           initial begin
                   clk = 0;
                   rstn = 1;
                   i_data = 0;
                   #20;
                   rstn = 0;

                   #30;
                   rstn = 1;
                   #20;
                   i_data = 8'hFA;
                   #20;
                   i_data = 8'hF0;
                   #20
                   i_data = 8'hF1;
                   #20
                   #10 $finish;
           end

           always #10 clk = !clk;

           flipflop flipflop(
                   .clk (clk),
                   .rstn(rstn),
                   .i_data(i_data),
                   .o_data(o_data)
           );

           initial begin
                   $dumpfile("flipflop.vcd");
                   $dumpvars();
           end
       endmodule

我的 D 触发器在这里就像一个组合电路.

My D flip flop functions like a combinational circuit here.

推荐答案

模拟器可能正在做这样的事情:

The simulator is probably doing something like this:

       initial begin
               clk = 0;
               rstn = 1;
               i_data = 0;
               #10;
               clk = !clk;
               #10;
               rstn = 0;
               clk = !clk;

               #10;
               clk = !clk;
               #10;
               clk = !clk;
               #10;
               rstn = 1;
               clk = !clk;
               #10;
               clk = !clk;
               #10
               i_data = 8'hFA; //Input updated
               clk = !clk;     //Clock event
                               //o_data assigned here
               #10;
               clk = !clk;
               #10;
               i_data = 8'hF0;
               clk = !clk;
               #20
               i_data = 8'hF1;
               #20
               #10 $finish;
       end

由于时钟事件在您的测试平台的每个时间步中最后发生，看起来触发器是立即分配的.您可能希望您的测试平台完全不受时钟控制，因此 Marty 使用 @(posedge...) 的建议将实现这一点.你也可以在一开始就推迟一次你的任务:

Since the clock event is occurring last in each time step from your testbench, it looks like the flop is being assigned immediately. You likely want your testbench to be entirely slaved off the clock so Marty's suggestion of using @(posedge...) will achieve this. You could also simply delay your assignments once at the very beginning:

       initial begin
               clk = 0;
               #1;
               rstn = 1;
               i_data = 0;
               #20;
               rstn = 0;

               #30;
               rstn = 1;
               #20;
               i_data = 8'hFA;
               #20;
               i_data = 8'hF0;
               #20
               i_data = 8'hF1;
               #20
               #10 $finish;
       end

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