模拟输出全为零 [英] Simulation output is all zeroes
问题描述
我的设计块和测试平台代码编译;然而,当我模拟时,我没有得到正确的输出.谁能告诉我我的代码哪里出错了?
My code for the design block and the testbench compiles; however, when I simulate, I'm not getting the correct output. Can anyone tell me where I'm going wrong in my code?
这是测试平台的代码:
module testbench;
reg [511:0]FROM_LS;
reg CLK;
reg [63:0]TO_IF_ID;
initial
begin
CLK= 0;
TO_IF_ID[63:0]=63'b0;
FROM_LS[511:480]= 32'b00011_00000_00100_01100_11100_10111_01;
FROM_LS[479:448]=32'b00_11000_00100_01111_11111_00011_10000;
end
always
begin
#10 CLK= ~ CLK;
//FROM_LS[511:448]= ~ FROM_LS[511:448];
$display("FROM_LS= %b", FROM_LS);
$display("TO_IF_ID= %b", TO_IF_ID);
end
endmodule
这里是设计块的代码:
module inst_line_buffer(input wire [511:0]from_LS,
input wire clk,
output reg [63:0]to_if_id);
parameter mem_size=16;
integer k;
reg [31:0] ilb[0:mem_size-1];
initial
begin
for (k = 0; k < mem_size ; k = k + 1)
begin
ilb[k] = 32'b00;
//$display ("ilb= %b",ilb[k]);
end
end
always @(posedge clk)
begin
ilb[0]= from_LS[511:480];
ilb[1]= from_LS[479:448];
ilb[2]= from_LS[447:416];
ilb[3]= from_LS[415:384];
ilb[4]= from_LS[383:352];
ilb[5]= from_LS[351:320];
ilb[6]= from_LS[319:288];
ilb[7]= from_LS[287:256];
ilb[8]= from_LS[255:224];
ilb[9]= from_LS[223:192];
ilb[10]= from_LS[191:160];
ilb[11]= from_LS[159:128];
ilb[12]= from_LS[127:96];
ilb[13]= from_LS[95:64];
ilb[14]= from_LS[63:32];
ilb[15]= from_LS[31:00];
to_if_id [63:32]= ilb[0];
to_if_id [31:0]= ilb[1];
$display("ilb= %b", ilb[1]);
end
endmodule
我期望 TO_IF_ID
的值应该是 0001100000001000110011100101110100110000010001111111110001110000
,但我得到零
I'm expecting that the value of TO_IF_ID
should be 0001100000001000110011100101110100110000010001111111110001110000
, but I'm getting all zeros.
推荐答案
当您在 testbench
模块上运行模拟时,TO_IF_ID
始终为 0,因为您只分配了一个在 initial
块中的时间 0 处为其赋值一次.如果您希望该值发生变化,则需要以某种方式对其进行驱动.
When you run a simulation on your testbench
module, TO_IF_ID
is always 0 because you only assigned a value to it once at time 0 in your initial
block. If you want the value to change, it needs to be driven somehow.
正如 Andy 在评论中指出的,您可能打算在测试平台中实例化 inst_line_buffer
模块.Verilog 不会神奇地为您做到这一点.但是,您应该将 TO_IF_ID
声明为 wire
而不是 reg
并将其从 initial
块中删除.
As Andy pointed out in a comment, you probably meant to instantiate the inst_line_buffer
module in your testbench. Verilog will not do this magically for you. But then, you should declare TO_IF_ID
as a wire
instead of a reg
and remove it from the initial
block.
module testbench;
reg [511:0]FROM_LS;
reg CLK;
wire [63:0]TO_IF_ID;
inst_line_buffer inst_line_buffer (
.from_LS (FROM_LS),
.clk (CLK),
.to_if_id (TO_IF_ID)
);
initial begin
CLK= 0;
FROM_LS[511:480]= 32'b00011_00000_00100_01100_11100_10111_01;
FROM_LS[479:448]=32'b00_11000_00100_01111_11111_00011_10000;
#500 $finish;
end
always
begin
#10 CLK= ~ CLK;
//FROM_LS[511:448]= ~ FROM_LS[511:448];
$display("FROM_LS= %b", FROM_LS);
$display("TO_IF_ID= %b", TO_IF_ID);
end
endmodule
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