使用正则表达式进行 Verilog 端口映射 [英] Using Regular Expressions for Verilog Port Mapping

问题描述

我有一个很长的端口映射，我想在其中替换一堆

I have a really long port map where I want to replace a bunch of

SignalName[i],

与

.SignalName(SignalName[i]),

我想我可以用正则表达式轻松地做到这一点，但我终生无法弄清楚如何做到这一点.有什么想法吗?

I think I can do this easily with regular expressions, but I can't for the life of me figure out how. Any ideas?

推荐答案

假设 SignalData 是包含您的端口映射信息的文件，以下内容将满足您的需求.

Assuming SignalData is the file containing your port map information, the following would do what you want.

sed -si 's/\([a-zA-Z]\+\)\(\[[^\]]*\]\)/\.\1(\1\2)/g' SignalData

在 sed 中 s 代表替换，第一对//之间的正则表达式用于匹配每一行.如果找到匹配，则在下一个/之间的表达式将替换匹配的内容.

In sed s stands for substitution, regex between the first pair of // is used to match against each line. If a match is found the expression between upto the next / is made to replace what was matched.

正则表达式说明

\([a-zA-Z]\+\) - Matches a series of alphabets (like SignalName) and captures it into
\1. If you want only the SignalName string to match, replace [a-zA-Z]\+ with SignalName.
\(\[[^\]]*\]\) - Matches the [some character] part and captures it into \2

最后我们使用这些捕获的字符串来构建所需的字符串.

Finally we use these captured strings to construct the desired string.

如果您想在运行文件之前对此进行试验，请使用 sed -s 而不是 sed -si.这将在标准输出上显示转换的结果，而无需实际更改文件

If you want to experiment with this before running on your file use sed -s instead of sed -si. That will show the results of the transformation on stdout, without actually changing the file

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