Verilog 范围必须以常量表达式为界 [英] Verilog range must be bounded by constant expression

问题描述

我无法弄清楚如何将此 VHDL 代码转换为 Verilog.

I'm having trouble figuring out how to translate this VHDL code to Verilog.

v_Upper     := r_Digit_Index*4 + 3;
v_Lower     := r_Digit_Index*4;
v_BCD_Digit := unsigned(r_BCD(v_Upper downto v_Lower));

if v_BCD_Digit > 4 then
  v_BCD_Digit := v_BCD_Digit + 3;
end if;

r_BCD(v_Upper downto v_Lower) <= std_logic_vector(v_BCD_Digit);

如果我尝试在 Verilog 中执行此操作，则会收到错误消息范围必须由常量表达式绑定".我理解错误，但我想不出解决这个问题的好方法.本质上，我想解析 r_BCD 的特定半字节，如果需要更新则更新它，然后将其写回我从中提取它的同一位置.二维数组在这里会更好吗?

If I try doing this in Verilog, I get the error, "Range Must be Bound by Constant Expression." I understand the error, but I can't figure out a good way to get around this. Essentially I want to parse a specific nibble of r_BCD, update it if it needs updating, then write it back into the same location that I pulled it from. Would a 2D array be better here?

这是导致问题的 Verilog 代码行:+

Here's the line of Verilog code causing the problem:+

r_BCD[r_Digit_Index*4 + 3:r_Digit_Index*4] <= w_BCD_Digit + 3;

推荐答案

在 verilog 中你不能有这样的变量选择.

In verilog you can not have a variable selection like that.

即r_BCD[r_Digit_Index*4 + 3:r_Digit_Index*4] 是不允许的.

自 2001 年以来，您可以使用特殊的 +: 语法进行可变部分选择.

Since 2001 you can do variable part-select using the special +: syntax.

例如:

r_BCD[r_Digit_Index*4 +: 4] 
   //[ index          +: width]  

有关详细信息，请参阅 Sutherland 2001 第 1-48 部分.

For more info see Sutherland 2001 part 1-48.

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