verilog中的二进制编码小数 [英] Binary coded decimals in verilog
本文介绍了verilog中的二进制编码小数的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!
问题描述
我为 BCD 编写了以下代码到七段.代码也编译 find 并模拟,但 num 的值不会超过 2.我不知道为什么会这样.代码如下:
I wrote the following code for BCD to seven segment. The code compiles find and simulates too but the value of num is not going beyond 2. I don't know why is that. Here is the code:
module BCDtoSeven_TOP
reg [3:0] num;
wire a,b,c,d,e,f,g;
BCDtoSeven s(num,a,b,c,d,e,f,g);
initial begin
num=1;
end
always @(num<=9) begin
#2 num=num+1;
end
endmodule
子模块:
module BCDtoSeven(num,a,b,c,d,e,f,g);
output a,b,c,d,e,f,g;
input [3:0] num;
assign a=(num==4 || num==5 || num==6 || num==7 || num==8 || num==9)? 1:0;
assign b=(num==2 || num==3 || num==5 || num==6 || num==7 || num==8 || num==9)? 1:0;
assign c=(num==2 || num==3 || num==8 || num==9 || num==7)? 1:0;
assign d=(num==4 || num==3 || num==5 || num==8 || num==9 || num==7)? 1:0;
assign e=(num==5 || num==3 || num==6 || num==8 || num==9)? 1:0;
assign f=(num==2 || num==1 || num==6 || num==8 )? 1:0;
assign g=(num==2 || num==3 || num==6 || num==8 || num==9 || num==5 )? 1:0;
endmodule
推荐答案
always @
块在其敏感度列表中的任何信号发生变化时都会被执行.num<=9
保持为真,所以块只执行一次.
The always @
block gets executed any time a signal in its sensitivity list changes. num<=9
remains true so the block only executes once.
使用时钟的替代方法可能如下所示:
An alternative using a clock might look like:
always @(posedge clk) begin
if(num <= 9) begin
num = num+1;
end
end
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