verilog 什么时候使用当前时隙的值,什么时候使用上一个时隙的值? [英] When does verilog use values from the current and when from the previous timeslot?
问题描述
这是一个简短的示例代码,让我很困惑.在 verilog 进程中使用当前或前一个模拟时隙的值的规则是什么?
Here is a short example code, which confused me. What is the rule to use values from the current or when from the previous simulation time-slot in verilog processes?
module test();
reg clk, rst, r1, r2, r3;
initial begin
clk = 0;
rst = 0;
r1 = 0;
r2 = 0;
r3 = 0;
@(posedge clk)
rst = 1;
end // initial
always #5 begin : clkgen
clk = ~clk;
end
/** TESTS **/
// PREVIOUS
always @(posedge clk) begin : proc_non_block
r1 = rst;
end
// CURRENT
always @(posedge clk or posedge rst) begin : proc_async
r2 <= rst;
end
// PREVIOUS
always @(posedge clk or negedge rst) begin : proc_async_neg
r3 <= rst;
end
endmodule // test
这是模拟的结果.(Questasim 10.4C)
Here is the result of the simulation. (Questasim 10.4C)
上面的实验表明,仅当给定信号在当前模拟时隙具有活动事件时,才使用给定信号的当前值.我对吗?有什么细节吗?
Experiments above shows me that the current value of a given signal is used only if the given signal has an active event at the current simulation time-slot. Am I right? Any details?
推荐答案
Verilog 总是 使用变量的当前值.此问题是在进行分配时更新当前值.由于您在解除对 clk
的 posedge
的阻塞的进程中使用阻塞赋值写入了 rst
,因此存在与其他块的竞争条件也在 clk 的 posedge
上解除阻塞.每个 always
进程何时解除阻塞,相对于 Initial
进程何时解除阻塞,将其分配给 rst 没有定义的顺序.因此,当您获得
rst ` 的 _old_ 值时,它会出现,因为分配尚未发生.
Verilog always uses the current value of variable. This issue is when the current value gets updated when making an assignment. Since you wrote to rst
with a blocking assignment in a process that unblocks on the posedge
of clk
, there is a race condition with other blocks that also unblock on the posedge
of clk. There is no defined ordering of when each always
process unblocks relative to when the Initial
process unblocks making its assignment to rst . So it appears as you get the _old_ value of
rst ` because the assignment has not happened yet.
一般规则是:每当一个进程写入时,对变量使用非阻塞赋值,另一个进程读取同一个变量,并且所有进程都同步到同一个时钟事件.
The general rule is: use non-blocking assignments to a variable whenever one process writes, and another process reads the same variable and all the process are synchronized to the same clock event.
这篇关于verilog 什么时候使用当前时隙的值,什么时候使用上一个时隙的值?的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!