电线声明后的localparam [英] localparam after wire declaration

问题描述

出于一个非常奇怪的原因(我们使用的脚本)，我需要能够在我在模块中声明电线和 regs 之后声明一个 localparam:

For a very strange reason (scripts we use) I need to be able to declare a localparam AFTER I declare wires and regs in a module:

module blah (clk, rst, in, out);

  input        clk;
  input        rst;
  input  [2:0] in;
  output [3:0] out;

  wire         res;

  localparam NUMBER=5;


...

这是合法的verilog代码吗?我也很感激文档中相关部分的链接.谢谢！

is this legal verilog code? I would also appreciate a link to the relevant seciton in the documentation. Thanks!

推荐答案

这是有效的 Verilog (2001).Verilog 2001 引入了 localparam，对于所有版本，在此上下文中使用参数在语法上仍然有效.localparam 表示不能被覆盖.

This is valid Verilog (2001). Verilog 2001 saw the introduction of localparam, for all versions it is still syntactically valid to use parameter in this context. localparam indicates that it can not be overridden.

用法可以在 23.10 Overriding module parameters 部分中看到"nofollow">SystemVerilog IEEE Std 1800-2012.

Usage can be seen in section 23.10 Overriding module parameters of SystemVerilog IEEE Std 1800-2012.

来自 IEEE 1800-2012:

From IEEE 1800-2012:

例如:

module generic_fifo
    #(MSB=3, LSB=0)        // parameter port list parameters
    (input  wire  [MSB:LSB] in,
     input  wire            clk, read, write, reset,
     output logic [MSB:LSB] out,
     output logic           full, empty );

  parameter   DEPTH=4; // module item parameter

  localparam FIFO_MSB = DEPTH*MSB;
  localparam FIFO_LSB = LSB;
    // These constants are local, and cannot be overridden.
    // They can be affected by altering the value parameters above

  logic [FIFO_MSB:FIFO_LSB] fifo;
  logic [LOG2(DEPTH):0] depth;

  always @(posedge clk or posedge reset) begin
    casez ({read,write,reset})
      // implementation of fifo
    endcase
  end
endmodule

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