什么时候在 VHDL 中分配信号? [英] When do signals get assigned in VHDL?

问题描述

考虑这个代码:

architecture synth of my_entity is
    signal a : std_logic;
begin

    a <= c and d;
    b <= a and c;

end synth;

第二行是要尊重 a 在其他进程中的变化还是所有信号都只在 架构 的末尾分配?

Is the second line going to respect that a changed in the other process or are all signals only at the end of architecture assigned?

推荐答案

小心你的术语.当你说a在另一个进程"中发生变化时，这在VHDL中具有特定含义(进程是VHDL中的关键字)，并且你的代码没有任何进程.

Careful with your terminology. When you say a changed in the other "process", that has a specific meaning in VHDL (process is a keyword in VHDL), and your code does not have any processes.

合成器会将您的代码视为:

Synthesizers will treat your code as:

a <= c and d;
b <= (c and d) and c;

模拟器通常会在第一次传递中分配 a，然后在第二次传递中分配 b 一个delta".delta 是一个无穷小的时间延迟，它发生在与初始分配相同的模拟时间.

Simulators will typically assign a in a first pass, then assign b on a second pass one 'delta' later. A delta is an infinitesimal time delay that takes place at the same simulation time as the initial assignment.

请注意，这是对实际情况的粗略概括……如果您需要完整的详细信息，请阅读随工具链提供的文档.

Note this is a gross generalization of what really happens...if you want full details, read up on the documentation provided with your tool chain.

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