触发器在两个信号的边沿触发 [英] Flip-Flop triggered on the edge of two signals

问题描述

我需要一个能够对两个不同信号的边缘做出反应的触发器.像这样:

I need a flip flop that reacts on the edges of two different signals. Something like this:

if(rising_edge(sig1)) then
    bit <= '0';
elsif(rising_edge(sig2)) then
    bit <= '1';
end if;

这样的触发器是否存在，或者我可以使用其他一些技术吗?我需要在 Xilinx Virtex-5 FPGA 上进行综合.谢谢

Does such a flip flop exist or is there some other technique i could use? I need this to be synthesizable on a Xilinx Virtex-5 FPGA. Thanks

推荐答案

在这种情况下，我通常会保持两个控制信号的延迟版本，并在每个控制信号的上升沿生成一个时钟宽度的脉冲信号.然后我会使用这些脉冲来驱动一个微小的 FSM 来生成位"信号.下面是一些 VHDL.

What I'd usually do in this case is to keep a delayed version of both the control signals and generate a pulse one clock wide at the rising edge of each signal. I'd then use these pulses to drive a tiny FSM to generate the 'bit' signal. Here's some VHDL below.

--                                         -*-vhdl-*-
--  Finding edges of control signals and using the
-- edges to control the state of an output variable
--

library ieee;
use ieee.std_logic_1164.all;

entity stackoverflow_edges is
  port ( clk  : in std_ulogic;
     rst  : in std_ulogic;
     sig1 : in std_ulogic;
     sig2 : in std_ulogic;
     bito : out std_ulogic );

end entity stackoverflow_edges;

architecture rtl of stackoverflow_edges is

  signal sig1_d1  , sig2_d1   : std_ulogic;
  signal sig1_rise, sig2_rise : std_ulogic;

begin 

  -- Flops to store a delayed version of the control signals
  -- If the contorl signals are not synchronous with clk,
  -- consider using a bank of 2 delays and using those outputs
  -- to generate the edge flags
  delay_regs: process ( clk ) is 
  begin 
    if rising_edge(clk) then
      if rst = '1' then 
        sig1_d1 <= '0';
        sig2_d1 <= '0';
      else
        sig1_d1 <= sig1;
        sig2_d1 <= sig2;
      end if;
    end if;
  end process delay_regs;


  -- Edge flags
  edge_flags: process (sig1, sig1_d1, sig2, sig2_d1) is
  begin
    sig1_rise <= sig1 and not sig1_d1;
    sig2_rise <= sig2 and not sig2_d1;
  end process edge_flags;

  -- Output control bit
  output_ctrl: process (clk) is
  begin 
    if rst = '1' then
      bito <= '0';
    elsif sig1_rise = '1' then
      bito <= '1';
    elsif sig2_rise = '1' then
      bito <= '0';
    end if;
  end process output_ctrl;

end rtl;

我对 verilog 更加熟悉，因此请仔细检查此 VHDL(感谢任何评论).

I'm a lot more comfortable in verilog, so double check this VHDL (any comments appreciated).

波形 http://img33.imageshack.us/img33/893/stackoverflowvhdlq.png

此代码假定时钟足够快以捕获所有控制信号脉冲.如果控制信号与时钟不同步，我会保留延迟控制信号的进一步延迟版本(例如 sig_d2)，然后从 制作标志sig_d1 和 sig_d2.

This code assumes that the clock is fast enough to capture all the control signal pulses. If the control signals are not synchronous with the clock, I'd keep a further delayed version of the delayed control signal (eg sig_d2) then make the flags from sig_d1 and sig_d2.

这篇关于触发器在两个信号的边沿触发的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！