等到上升边缘(clk)与如果上升边缘(时钟) [英] wait until rising_edge(clk) vs if rising_edge(clk)

问题描述

我在 VHDL 中遇到了两种风格的流程语句.

I came across two styles of process statement in VHDL.

process(clk)
begin
    if rising_edge(clk)
....do something....

另一个是

process
begin    
    wait until rising_edge(clk)
    ....do something....

每种方法的优缺点是什么.

What are the pros and cons of each method.

推荐答案

假设第二个例子的 ... 部分没有任何 wait 语句，两个形式在语义上是等价的.

Assuming the ... part of the second example does not have any wait statement, the two forms are semantically equivalent.

它们在模拟中的行为相同.

They will behave identically in simulation.

然而，第一种形式是推荐的综合风格，许多人认为更易读.

However, the first form is the recommended style for synthesis and will be deemed more readable by many.

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