VHDL 引用的上下文元素 [英] VHDL referenced context element

查看:18
本文介绍了VHDL 引用的上下文元素的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

我正在用 VHDL 实现一些东西,但我不明白我得到的错误:

I am implementing something in VHDL, and I don`t understand the errors that I get:

library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;

entity LogicF is
    port(A,B,C:in std_logic; Y:out std_logic);
end LogicF;
architecture STRUCTURAL of LogicF is
signal notA, notB, andSign:std_logic;
begin  
    inv1:inverter port map (i=>A,o=>notA);
    inv2:inverter port map (i=>B,o=>notB);
    si1:and2 port map (i1=>notA, i2=>notB, o=>andSign);
    sau1:or2 port map (i1=>andSign, i2=>C, o=>Y);
end STRUCTURAL;

错误:(3,10):找不到引用的上下文元素.错误:(8,1):找不到引用的实体声明LogicF"

Error: (3,10): Cannot find referenced context element. Error: (8,1): Cannot find referenced entity declaration "LogicF"

推荐答案

正如 Brian 在第 3 行指出的那样,字符 10 (3,10) 是 中单词 primitive 的第一个字符使用.work.primitive.all;.该包似乎不在工作库中.

As Brian points out Line 3, Character 10 (3,10) is the first character of the word primitive in use.work.primitive.all;. It seems the package hasn't been in the working library.

%% ghdl -a LogicF.vhdl
LogicF.vhdl:3:10:在库work"中找不到主要单元primitive"
ghdl:编译错误
%%

%% ghdl -a LogicF.vhdl
LogicF.vhdl:3:10: primary unit "primitive" not found in library "work"
ghdl: compilation error
%%

关于哪个工具来自(8,1)处的第二个错误的问题,实体LogicF没有成功分析并且没有放入工作库中.

The question about which tool comes from the second error at (8,1), the entity LogicF did not successfully analyze and wasn't placed in the working library.

IEEE Std 1076(LRM)、设计单位及其分析分析顺序:

IEEE Std 1076 (the LRM), Design units and their analysis, Order of analysis:

如果在尝试分析设计单元时检测到任何错误,然后尝试的分析被拒绝并且没有任何影响在当前工作库上.

If any error is detected while attempting to analyze a design unit, then the attempted analysis is rejected and has no effect whatsoever on the current working library.

第二个错误来自实体 LogicF 不存在于引用的库中.

The second error comes from the entity LogicF not being present in a referenced library.

(LRM)相同部分(11.4 -1993,13.5 -2008):

(The LRM) same section (11.4 -1993, 13.5 -2008):

定义设计单元分析顺序的规则是可见性规则的直接后果.特别是:

The rules defining the order in which design units can be analyzed are direct consequences of the visibility rules. In particular:

a.  A primary unit whose name is referenced within a given design unit must be analyzed prior to the analysis of the given design unit.

b.  A primary unit must be analyzed prior to the analysis of any corresponding secondary unit.  

实体是主要单元 (LogicF),架构 (STRUCTURAL) 是次要单元.

An entity is a primary unit (LogicF) an architecture (STRUCTURAL) is a secondary unit.

当我使用 ghdl 分析您的设计文件"时,它在第一个错误后退出.在这种情况下,因为第二个设计单元是次要单元,第一个失败足以阻止分析成功.如果还有更多不相关的设计单元,如果证明它们没有错误(并且不依赖于包原语),他们的分析可以继续进行.

When I used ghdl to analyze your design 'file' it quit after the first error. In this case because the second design unit was a secondary unit, the first failing was sufficient to stop analysis from succeeding. If there were further unrelated design units their analysis could have continued should they have proven to be error free (and didn't depend on the package primitives).

错误消息中缺少对任何假设的解释,这些假设通常可以在工具实现的文档中找到.

What's missing from the error messages are explanations of any assumptions, which are typically found in the tool implementation's documentation.

为了在他的评论中回答 Brian 的问题,错误消息的格式来自 Aldec,显然是 Aldec-HDL 工具(谷歌 有时很有用).

To answer Brian's question in his comment the format of the error message is from Aldec, apparently the Aldec-HDL tool (Google is useful betimes).

这是一个专业的好奇问题,Brian 是 ghdl 开发人员之一.VHDL 没有要求错误要求您不要分析在同一设计文件中找到的更多设计单元.这是一个实现细节,现在我们知道 Aldec 做了什么.

His was a professional curiosity question, Brian is one of the ghdl developers. There is no requirement VHDL that an error requires you to not analyze further design units found in the same design file. It's an implementation detail, where now we know what Aldec does.

除了与客户共享文档外,Aldec 不会共享文档,否则很难寻求第三方帮助.您会看到很多大学都发布了有关使用 Aldec 工具的教程.

Aldec doesn't share documentation other than with customers which otherwise makes it hard to seek third party help. You see a lot of universities publish tutorials on using Aldec tools.

我在识别供应商的另一个第三方论坛中发现了错误消息.

I found the error message in another third party forum where the vendor was identified.

这篇关于VHDL 引用的上下文元素的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

查看全文
登录 关闭
扫码关注1秒登录
发送“验证码”获取 | 15天全站免登陆