在 VHDL 过程中写入后读取 [英] Write followed by Read in VHDL process

问题描述

以下代码是一个非常简单的 VHDL 程序.

The following code is for a very simple program in VHDL.

entity ent is
    port(
        clk: in std_logic;
        out_value: out std_logic;
    );
end entity ent;

architecture ent_arch of ent is
    signal counter: std_logic_vector(3 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            counter <= counter + 1;
            if counter = 10 then
                counter <= (others => '0') ;
            end if;
        end if;
    end process;
end ent_arch;

想象一下counter = 9，然后我们进入if语句(ifrising_edge(clk)).第一个语句 counter <= counter + 1 将 10 分配给 counter.我的问题是if 语句(如果 counter = 10)在这个入口还是在流程的下一个入口被评估为 true ?".换句话说，对于进程这个入口的这个比较，counter = 10 是不是因为前面的语句?"

Imagine counter = 9 and we enter in the if statement (if rising_edge(clk)). The first statement counter <= counter + 1 will assign 10 to counter. My question is "Is the if statetement (if counter = 10) evaluted as true in this entrance or in the next entrance of the process?". In other words "For this comparison in this entrance of the process, is counter = 10 due to the previous statement?"

非常感谢您的回答！

推荐答案

信号分配总是被延迟.您没有使用 after 关键字明确指定延迟，因此分配会延迟一个增量周期(与 after 0 fs 相同).这意味着，该语句右侧的表达式的值:

Signal assignments are always delayed. You didn't specified a delay explicitly using the after keyword, thus the assignment is delayed for one delta cycle (same as after 0 fs). That means, that the value of the expression on the right side of this statement:

counter <= counter + 1;

将在下一个模拟周期开始时分配给counter.

will be assigned to counter at the beginning of the next simulation cycle.

但是，流程中的所有剩余语句都在当前模拟周期中执行.因此，这个计数器值的读取，

But, all remaining statements in your process, are executed in the current simulation cycle. Thus, this read of the counter value,

if counter = 10 then

仍将使用旧值，因此，当计数器在时钟上升沿已为 10 时将被重置.计数器从 0 到 10 计数.

will still use the old value, so that, the counter will be reseted when it is already 10 at the rising clock edge. The counter counts from 0 to 10 inclusive.

至少一个增量周期的延迟，可以轻松地交换寄存器的内容:

The delay of at least one delta cycle, easily allows to swap the content of registers:

-- within declarative part of architecture
signal reg_a, reg_b : std_logic;

-- within architecture body
process(clock)
begin
  if rising_edge(clock) then
    reg_a <= reg_b;
    reg_b <= reg_a;  -- assign old value of reg_a ! 
  end if;
end process;

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