VHDL:变量和过程 [英] VHDL: variable and process

问题描述

我正在研究 VHDL，我发现一件特别难以理解的事情，因为 VHDL 是一种 HDL，在我看来，它描述的一切都应该能够转换成电路.但是这怎么会发生在变量和过程上呢?有没有什么电路可以实现变量和过程?你能给我举个例子吗?谢谢

解决方案

包含变量的过程当然可以转换为电路.

这里有几个简单的例子.

进程(clk)变量 Q : std_logic_vector(7 downto 0);开始如果rising_edge(clk) 那么如果 En = '0' 那么问:= D;万一;万一;输出 <= Q;结束过程；

在每个时钟周期，如果En(Enable)输入为低电平，则输入数据D存入变量Q；否则什么都不会发生(并且变量保持其旧值).这是一个非常特殊的电路；一个带使能的 8 位寄存器；在旧数据手册中查找 74LS377 以在 TTL 中看到相同的电路.

注意时钟if"语句与 En 语句分开，并包围它.综合工具寻找他们知道如何翻译的特定模式，这就是其中之一.如果您有任何软件经验，您可能会想将它们结合起来:ifrising_edge(Clk) and En = '0' then ... - 在模拟中，您会得到完全相同的行为.>

然而，一些综合工具可能无法识别这种模式，并且可能会报告错误而不是生成硬件.(合成工具在不断改进，所以你现在可能很幸运).该工具的文档(例如 Xilinx综合和仿真设计指南") 应该描述什么是可能的，什么是不可能的. 不幸的是，它停留在 1995 年的实践中，并且包含一些真正可怕的 VHDL 示例.

进程(clk)变量计数:整数范围 0 .. 255 := 0;-- 进程第一次启动时设置为 0开始如果rising_edge(clk) 那么计数 := 计数 + 1 mod 256;万一;输出:=计数；结束过程；

注意变量和信号一样，不需要是逻辑类型；整数、数组和记录(有一些限制)是可合成的；浮动通常不是(尽管随着工具的改进这种情况正在发生变化).请注意，我限制了整数的范围，以获得 8 位计数器.

对于整数，您还需要明确指定当它们溢出时会发生什么(就像我在这里所做的那样) - 否则您将在模拟中出错.但是，指定明显的行为(如此处)不应该花费任何额外的硬件.使用其他数字类型，如 numeric_std.unsigned，工具就没有那么挑剔了.

我简化了一点；通常在典型流程中会有一个 Reset 子句来让您控制启动行为，但这些示例是真实的，应该有效.

I am studying VHDL and I found one thing particularly difficult to understand, since VHDL is a HDL, in my humble opinion, everything it describe should be able to be converted into a circuit. But how could this happen to variable and process? Is there any circuit that can realize variable and process? Can you give me an example of this? Thanks

解决方案

Processes containing variables certainly can be converted into circuits.

Here are a couple of simple examples.

Process(clk)
Variable Q : std_logic_vector(7 downto 0);
begin
  if rising_edge(clk) then
     if En = '0' then
        Q := D;
     end if;
  end if;
  Output <= Q;
end process;

In every clock cycle, if the En (Enable) input is low, the input data D is stored in the variable Q; otherwise nothing happens (and the variable keeps its old value). This is a very specific circuit; an 8-bit register with enable; look up the 74LS377 in an old data book to see the same circuit in TTL.

Notice that the clock "if" statement is kept separate from the En statement, and surrounds it. Synthesis tools look for specific patterns that they know how to translate, and this is one of them. If you have any software experience you might be tempted to combine them : if rising_edge(Clk) and En = '0' then ... - and in simulation you would get exactly the same behaviour.

However some synthesis tools may not recognise this pattern, and may report errors instead of generating hardware. (Synthesis tools are continually improving, so you might be lucky nowadays). The tool's documentation (e.g. Xilinx "synthesis and simulation design guide") ought to describe what is and isn't possible. [edit:] unfortunately it is stuck around 1995 practices and contains some truly horrible examples of VHDL.

Process(clk)
Variable Count : Integer range 0 .. 255 := 0;    -- set to 0 when process first starts
begin
  if rising_edge(clk) then
     Count := Count + 1 mod 256;
  end if;
  Output := Count;
end process;

Notice that variables, like signals, do not need to be logic types; integers, arrays and records (with some restrictions) are synthesisable; floats usually are not (though this is changing as tools improve). Notice that I limited the range of the integer, to get an 8-bit counter.

With integers, you also need to explicitly specify what happens when they overflow (as I did here) - otherwise you will get errors in simulation. However, specifying the obvious behaviour (as here) should not cost any additional hardware. And using other numeric types like numeric_std.unsigned, the tools are not so fussy.

I have simplified a little; usually there is a Reset clause in a typical process to let you control startup behaviour, but these examples are real and ought to work.

这篇关于VHDL:变量和过程的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！