VHDL中的过程是可重入的吗? [英] Is process in VHDL reentrant?

问题描述

在VHDL中是否可以连续运行两个或多个进程?

Is it possible two or more sequential run for a process in VHDL?

如果未完成过程的顺序执行而又发生了另一个事件(在灵敏度信号列表上)，将会发生什么?

What will happen if another event happen (on sensitivity signal list) while the sequential execution of a process is not completed ?

是否可能或者我想到的VHDL模型完全错误?

Is it possible or my VHDL model in mind for process is completely wrong?

推荐答案

进程运行时不会发生任何事件！

No event will ever occur while a process is running!

当一个进程被事件唤醒时，它会运行到完成(结束进程")或显式的"wait"语句，然后进入睡眠状态.从概念上讲，这需要零时间.这意味着，如果您的流程中存在循环，则循环将完全展开，并且在您进行综合时，您将生成足够的硬件来并行运行每个迭代.另外，任何过程，函数等都需要零时间-除非它们包含明确的"wait"语句(在这种情况下，过程在"wait"处挂起，就像过程已被内联一样).

When a process is woken by an event, it runs to completion ("end process") or an explicit "wait" statement, and goes to sleep. This takes, notionally, ZERO time. Which means that if you have loops in your process, they are effectively unrolled completely, and when you synthesise, you will generate enough hardware to run EVERY iteration in parallel. Also, any procedures, functions etc, take zero time - unless they contained an explicit "wait" statement (in which case the process suspends at the "wait", as if the procedure had been inlined).

在整个过程中，所有信号均具有其在唤醒过程中所具有的原始值，并且所有信号分配都被存储起来，以备以后使用. (变量会立即更新；该过程中的后续语句将看到新值).

Throughout this process, all signals have the value they originally had when the process woke up, and any signal assignments are stored up, to happen later. (Variables update immediately; later statements in the process see the new value).

当进程挂起(在等待"或结束进程"时)，直到所有其他进程也挂起，什么也不会发生. (但请记住，它们都需要零时间！).如果某个进程在结束进程"中挂起，则在其敏感度列表将其唤醒时，它将从头开始重新启动.如果它在显式的等待"中挂起，则该等待"将指定一个事件或将来的时间，它将在等待"之后重新启动它. (注:1:请勿在同一过程中混合使用灵敏度列表和等待样式！2:等待直到某个事件可综合(尽管某些工具可能会反对)；等待一段时间仅是模拟)

When the process suspends (at "wait" or "end process"), nothing happens until ALL the other processes also suspend. (But remember they all take zero time!). If a process suspends at "end process" it will restart from the beginning when its sensitivity list wakes it up. If it suspends at an explicit "wait", that "wait" will specify an event or future time, which will restart it after the "Wait". (NOTES: 1 : do not mix the sensitivity list and Wait styles in the same process! 2: Wait Until some event is synthesisable (though some tools may object) ; Wait for some time is simulation only)

完成所有信号分配后.由于所有过程都处于睡眠状态，因此消除了所有比赛条件和计时危险.其中一些分配(例如时钟为"1")将导致事件安排在对其敏感的进程上.

THEN all the signal assignments are performed. Since all processes are asleep, this eliminates all race conditions and timing hazards. Some of these assignments (like '1' to a clock) will cause events to be scheduled on processes sensitive to them.

完成所有信号分配后，时间步长将向前移动一个无限短的滴答声(称为增量周期)，然后唤醒所有具有计划事件的进程.

After all the signal assignments are done, the time steps forward one infinitely short tick (called a delta cycle), and then all the processes with scheduled events are woken.

这一直持续到发生增量周期(在该周期中未安排任何新事件)，最后仿真可以按实时步长进行.

This continues until a delta cycle occurs in which NO new events are scheduled, and finally the simulation can advance by a real time step.

因此

process(clk)
begin
if rising_edge(clk) then
   A <= B;
   B <= A;
end if;
end process;

在VHDL中是无害的.

is hazard-free in VHDL.

如果您需要使用Verilog，请注意，其中某些情况会以不同的方式发生，并且您不能在模拟结果中依赖相同级别的可预测性.

If you ever need to use Verilog, be aware that some of this happens differently there, and you cannot rely on the same level of predictability in simulation results.

在综合中，我们当然会生成硬件，这将需要一些实时时间才能执行此过程.但是，综合和后端工具(布局和布线)可以保证忠实地遵守此模型，或者失败并报告失败的原因.例如，他们将累加所有实际延迟，并验证总和是否小于指定的时钟周期. (除非您将时钟速度设置得太高！).

In synthesis, of course, we generate hardware which will take some real time to execute this process. However, the synthesis and back-end tools (place and route) guarantee to either obey this model faithfully, or fail and report why they failed. For example, they will add up all the real delays and verify that the sum is less than your specified clock period. (Unless you have set the clock speed too high!).

因此，只要工具报告成功(并且您正确设置了时钟速度等时序约束)，就可以假装上述零时间"模型为真，并且真实的硬件行为将与仿真相匹配.保证，禁止工具错误！

So the upshot is, as long as the tools report success (and you are setting the timing constraints like clock speed correctly) you can pretend the above "zero time" model is true, and the real hardware behaviour will match the simulation. Guaranteed, barring tool bugs!

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