在带有变量的 VHDL 中使用 FOR 循环 [英] Using FOR loop in VHDL with a variable

问题描述

是否有任何可能的方法以以下形式创建 for 循环:

Is there any possible way to create a for loop in the form:

for i in 0 to some_var loop
    // blah,blah
end loop;

如果没有，有没有其他方法可以创建相同的循环?由于 While 循环允许使用变量作为限制，但它们在我的项目中无法合成.

If not, is there any alternative way to create the same loop? Since While loops allows to use variable as the limit, but they are not synthesizeable in my project.

提前致谢，

博扬·马托夫斯基

推荐答案

该变量适用于测试平台应用程序.

The variable works just fine for testbench applications.

对于综合，您可以通过使用静态范围和退出条件来获得相同的效果.将范围设置为您需要的最大值.

For synthesis you can get the same effect by using a static range and an exit condition. Set the range to be the maximum you will need.

for i in 0 to MAX_VALUE loop
  exit when i = some_var ;
  // blah,blah
end loop;

如果您的综合工具对此感到窒息，请提交错误报告.1076.6-1999 和 1076.6-2004(VHDL RTL 综合标准)都表明，具有静态范围的for"循环支持退出条件.您可能会发现有关使用循环标签 (1076.6-1999) 的支持问题，表明它不受支持.

If your synthesis tool chokes on this, file a bug report. Both 1076.6-1999 and 1076.6-2004 (VHDL RTL Synthesis Standards) indicate that exit conditions are supported for "for" loops with a static range. You may find support issues with respect to using a loop label (1076.6-1999) indicates it is not supported.

如果您发现错误(或缺乏支持)并且不报告它，您的供应商会认为这是您不关心的功能，因此不会投资更改他们的工具.

If you find a bug (or lack of support) and do not report it, your vendor will think it is a feature you don't care about, and hence, will not invest in changing their tool.

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