VHDL“用于"循环空范围 [英] VHDL "For" Loop Null Range
问题描述
我已经在这个问题上停留了几个小时,看来我无法通过搜索找到解决方案,即在这里或在Google上都找不到任何东西.
I've been stuck at this problem for some hours now, and it seems I can't find the solution by searching i.e. didn't find anything here or on Google.
这是我的代码:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std;
USE work.arrays.ALL;
ENTITY parallel IS
PORT (clk:IN std_logic; text:IN INT_ARRAY(119 DOWNTO 0); result:OUT INT_MATRIX_2D);
END parallel;
ARCHITECTURE arch OF parallel IS
COMPONENT unit_comparator IS
PORT (letter:IN integer; difference:OUT integer);
END COMPONENT;
SIGNAL temp: INT_MATRIX_2D := (others => (others => 0));
SIGNAL temp_differences: INT_ARRAY(119 DOWNTO 0) := (others => 0);
BEGIN
PROCESS(clk)
BEGIN
IF(rising_edge(clk))THEN
FOR index IN 119 TO 1 LOOP
temp(temp_differences(index))(temp_differences(index - 1)) <=
temp(temp_differences(index))(temp_differences(index - 1)) + 1;
END LOOP;
result <= temp;
END IF;
END PROCESS;
wiring_loop: FOR index IN 119 DOWNTO 0 GENERATE
wiring_unit: unit_comparator PORT MAP (text(index), temp_differences(index));
END GENERATE;
END arch;
您看到" FOR index IN 119 TO 1 LOOP "吗?
You see that "FOR index IN 119 TO 1 LOOP" ?
编译器发出"范围119到0为 Null "警告(毫无疑问,整个过程都没有按预期的那样工作),我似乎有问题理解.如果在循环的每一步中都有一个分配给索引"的整数,它怎么会变成空值(它说它发生在每一步!).我需要一个坚定的理解,而不是一个简单的解决方案. (注意:所有使用的模块和软件包均已测试并且可以正常工作!)
The compiler gives a "Range 119 to 0 is Null" warning (no doubt the whole thing doesn't work as it should), which I seem to have a problem understanding. If there is an integer assigned to "index" at each step through the loop, how can it become null (and it says it happens at every step!). I need a firm understanding rather than a plain solution to this. (Note: All of the modules and packages used are tested and work properly!)
谢谢!
推荐答案
范围需要一个与其限制相对应的方向.您需要119 downto 1
或1 to 119
. 119 to 1
不是适合迭代的范围.
Ranges need a direction that corresponds to their limits. You want 119 downto 1
or 1 to 119
. 119 to 1
is not a range that is suitable for iterating through.
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