vhdl quartus:范围的左边界必须是常数 [英] vhdl quartus : left bound of range must be a constant

问题描述

有没有办法在 std_logic_vector 中使用变量(信号)而不是使用常量，例如:

Is there any way to use a variable(signal) inside the std_logic_vector instead of using a constant, e.g :

dout((8*index + 7) downto 8*index) <= "00000001";

在这个例子中，信号是 index
提前致谢

in this example the signal is index
thanks in advance

推荐答案

假设信号或变量 index 是整数类型，应该可以正常工作.如果 index 是 std_logic_vector 类型的信号或变量，则需要将其转换为整数.

Assuming the signal or variable index is of type integer, that should work fine. If index is a signal or variable of type std_logic_vector, you'll need to convert it to an integer.

看下面的简单例子(刚刚在我的模拟器中愉快地编译):

See the following simple example (which just now compiled happily in my simulator):

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity thingy is
    port(clk : in std_logic;
           I : in std_logic_vector(3 downto 0);
           O : out std_logic_vector(15 downto 0);
           P : in std_logic_vector(1 downto 0));
end entity thingy;

architecture behav of thingy is
begin
    process (clk)
    begin
      if (clk = '1' and clk'event) then
        O(to_integer(unsigned(P))*4 + 3 downto to_integer(unsigned(P))*4) <= I;
      end if;
    end process;
end architecture behav; --thingy

请注意，此示例依赖于使用 numeric_std 而不是概要包.

Note that this example relies upon using numeric_std rather than the synopsis packages.

Brian Drummond 提出了一个很好的观点，即它可能不会合成，但如果没有合成，那么您可能应该提交错误报告.

Brian Drummond makes a good point that it is possible that it won't synthesize, but if it doesn't then you should probably file a bug report.

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