VHDL - DE0 - QUARTUS II PLL 未在 modsim 中显示输出 [英] VHDL - DE0 - QUARTUS II PLL not showing output in modsim

问题描述

我正在尝试使用锁相环为 VGA 控制器生成时钟.我运气不好，决定制作自己的时钟，然后工作正常.我让 VGA 控制器工作.回到 PLL，虽然我仍然无法选择 PLL 来为我提供输出.我做了一个小测试模型来模拟它.

Hi I am trying to use a phased lock loop for clock generation for a VGA controller. I had no luck and decided to make my own clock which then worked fine. I got the VGA controller working. Going back to PLL's though I still can't get a PLL selected to give me an output. I have made a little test model to simulate it.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY PLL4 IS 
PORT    (
        clk         :   IN std_logic;
        a               :   IN std_logic;
        rst         :   IN  std_logic:='0';
        x               :   OUT std_logic
        );
END ENTITY PLL4;

ARCHITECTURE A1 OF PLL4 IS
COMPONENT PLL_4 IS
PORT(
    clk_in_clk  : in  std_logic; -- clk
    rst_reset   : in  std_logic; -- reset
    clk_out_clk : out std_logic  -- clk
    );
END COMPONENT PLL_4;
SIGNAL clk25    :   std_logic;
BEGIN
CLK_25 : PLL_4 PORT MAP (clk,rst,clk25);
x <= a and clk25;

END ARCHITECTURE A1;

当我用 mod sim 模拟时，我得到以下内容

When I simulate this with mod sim I just get the following

我从未看到 PLL 时钟输出.谁能给我一些建议.

I never see the PLL clock output. Can anyone give me some advice on this.

--更新--添加来自 CLK_25 的信号后:PLL 我现在在 Modsim 上得到以下信息.第一个连接到实例化罚款以及一个到 clk_in_clk 的 clk，但值 clk_out_clk 会改变.见下文:

--Update-- After adding the signals from the CLK_25 : PLL I now get the following on Modsim. The rst connects through to the instantiation fine as well a clk to clk_in_clk, but the value clk_out_clk ever changes. See below:

这让我觉得我遇到的问题是用 Qsys 创建的 PLL 模型.Qsys 生成的 .vhd 中包含的模型如下:

This makes me think the problem I'm having is with the PLL model created with Qsys.The model contained in the .vhd generated by Qsys is below:

-- PLL_4.vhd

-- Generated using ACDS version 13.0sp1 232 at 2016.02.09.16:46:16

library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;

entity PLL_4 is
port (
    clk_in_clk  : in  std_logic := '0'; --  clk_in.clk
    rst_reset   : in  std_logic := '0'; --     rst.reset
    clk_out_clk : out std_logic         -- clk_out.clk
);
end entity PLL_4;

architecture rtl of PLL_4 is
component PLL_4_altpll_0 is
    port (
        clk       : in  std_logic                     := 'X';             -- clk
        reset     : in  std_logic                     := 'X';             -- reset
        read      : in  std_logic                     := 'X';             -- read
        write     : in  std_logic                     := 'X';             -- write
        address   : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- address
        readdata  : out std_logic_vector(31 downto 0);                    -- readdata
        writedata : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
        c0        : out std_logic;                                        -- clk
        areset    : in  std_logic                     := 'X';             -- export
        locked    : out std_logic;                                        -- export
        phasedone : out std_logic                                         -- export
    );
end component PLL_4_altpll_0;

begin

altpll_0 : component PLL_4_altpll_0
    port map (
        clk       => clk_in_clk,  --       inclk_interface.clk
        reset     => rst_reset,   -- inclk_interface_reset.reset
        read      => open,        --             pll_slave.read
        write     => open,        --                      .write
        address   => open,        --                      .address
        readdata  => open,        --                      .readdata
        writedata => open,        --                      .writedata
        c0        => clk_out_clk, --                    c0.clk
        areset    => open,        --        areset_conduit.export
        locked    => open,        --        locked_conduit.export
        phasedone => open         --     phasedone_conduit.export
    );

end architecture rtl; -- of PLL_4

推荐答案

我无法直接模拟您的 VHDL 代码，因为您没有发布 PLL_4_altpll_0 的代码.因此，我使用 Quartus-II 的 MegaWizard 插件管理器创建了一个合适的 PLL.无论如何，如果我直接在 ModelSim 中模拟 PLL4 实体，并在信号 clk 和 1 上应用时钟信号 a，我得到和你一样的输出:clk25 未定义.

I could not directly simulate your VHDL code, because you didn't posted the code of PLL_4_altpll_0. Thus, I created an appropiate PLL with the MegaWizard Plugin Manager of Quartus-II. Anyway, if I directly simulate the PLL4 entity within ModelSim and apply a clock on signal clk as well as 1 to signal a, I get the same output as you: clk25 is undefined.

但如果我使用单独的测试平台，它会按预期工作.您必须在 Quartus II 中设置测试平台，菜单分配 -> 设置 -> 仿真 -> 编译测试平台 -> 测试平台 -> 新建.这是我的测试平台代码.应用重置是可选的，因此我将其保留为 0.

But if I use a separate testbench, it works as expected. You have to setup the testbench within Quartus II, menu Assignements -> Settings -> Simulation -> Compile test bench -> Test Benches -> New. Here is my testbench code. Applying a reset is optional, so I left it 0.

library ieee;
use ieee.std_logic_1164.all;

entity PLL4_tb is
end entity PLL4_tb;

architecture sim of PLL4_tb is

  -- component ports
  signal clk : std_logic := '1';
  signal a   : std_logic;
  signal rst : std_logic;
  signal x   : std_logic;

begin  -- architecture sim

  -- component instantiation
  DUT: entity work.PLL4
    port map (
      clk => clk,
      a   => a,
      rst => rst,
      x   => x);

  -- clock generation
  clk <= not clk after 10 ns;

  -- waveform generation
  WaveGen_Proc: process
  begin
    rst <= '0'; -- no reset required
    a   <= '1';
    wait;
  end process WaveGen_Proc;
end architecture sim;

这是模拟输出:

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