VHDL Quartus II上的Shift Right(srl)错误 [英] Shift Right (srl) going wrong on VHDL Quartus II

问题描述

我正在尝试在Quartus II上制作一个8位的顺序乘法器.我完成了所有模块的所有仿真，但是其中一个显示了VWF仿真上的错误. sum_reg块在很小的时间间隔内进行了无限移位.

I'm trying to make a 8-bit Sequential Multiplier on Quartus II. I did all the simulations of all blocks, but one is showing error on the VWF simulation. The sum_reg block it's doing a infinite shift in a very small time interval.

在波形模拟的深蓝色"部分中，在o_DOUT上，这是直到MSB到达LSB为止，移位才变为无限大的时间.下图显示了模拟的深蓝色部分中发生的情况:

In the "dark blue" part of waveform simulation, on o_DOUT, it's when the shift gones infinite until the MSB goes to the LSB. The image below shows what happens in the dark blue part of the simulation:

有人知道会发生什么吗?

Someone know what's happen?

代码下方:

求和寄存器(模拟出错):

Sum register(where the simulation goes wrong):

 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;

 entity sum_register is 
 port (
     i_DIN   : in UNSIGNED(8 DOWNTO 0);
     i_LOAD  : in STD_LOGIC;
     i_CLEAR : in STD_LOGIC;
     i_SHIFT : in STD_LOGIC;
     o_DOUT  : buffer UNSIGNED(15 downto 0)
 );
 end sum_register;

 architecture arch_1 of sum_register is 
 begin 
     process(i_CLEAR,i_LOAD,i_SHIFT, i_DIN)
     begin
        IF (i_CLEAR = '1') THEN
            o_DOUT <= "0000000000000000";
        ELSIF (i_LOAD = '1') THEN
            o_DOUT(15 downto 7) <= i_DIN;
        ELSIF (i_SHIFT = '1') THEN
             o_DOUT <= o_DOUT SRL 1;
        END IF;
      end process;
end arch_1;

推荐答案

您需要在电路中使用时钟信号以使其同步，您将需要在实体中输入如下内容:

You need to use a clock signal in the circuit to make this synchronous, you will need an input in your entity like this:

i_CLOCK : in STD_ULOGIC;

在此之后，您需要使您的过程对时钟敏感:

After this you will need to make your process sensitivy to the clock:

process(i_CLOCK)

您的架构将更改为此:

 architecture arch_1 of sum_register is
  SIGNAL r_DOUT : unsigned(15 downto 0);
 begin
     process(i_CLOCK)
     begin
     IF rising_edge(i_CLOCK) THEN
        IF (i_CLEAR = '1') THEN
            r_DOUT <= "0000000000000000";
        ELSIF (i_LOAD = '1') THEN
            r_DOUT(15 downto 8) <= i_DIN;
        ELSIF (i_SHIFT = '1') THEN
              r_DOUT <= r_DOUT SRL 1;
        END IF;
      END IF;
      end process;
      o_DOUT <= r_DOUT;
end arch_1;

使用这种架构，您将需要一个无符号信号来为输出o_DOUT分配属性，从而可以将o_DOUT输出再次更改为输出类型(而不是缓冲区).

With this architecture you will need a unsigned signal to make atribution for your output o_DOUT, with this you can change your o_DOUT output to output type again (not buffer).

注意:所有模块的时钟信号必须相同！

NOTE: The clock signal needs to be the same for all blocks!

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