VHDL 错误代码 10500 [英] VHDL Error Code 10500

问题描述

Vhdl 新手，我正在尝试制作 6 到 64 位解码器.我编写了一个功能正常的 3 到 8 个解码器，我需要使用它(准确地说是其中的 9 个)来制作 6 到 64 个.我不断收到 10500 错误代码，在我声明组件的端口映射和";"在行尾.

New to Vhdl and I'm trying to make a 6 to 64 decoder. I have a functioning 3 to 8 decoder written and I need to use that (9 of them to be exact) to make the 6 to 64. I keep getting the 10500 error code around where I declare my port map for the component and the ";" at the end of the line.

    library ieee;
Use ieee.std_logic_1164.all;

entity dec6to64 is
    port (w0,w1,w2,w3,w4,w5, En : in std_logic;
            f : out std_logic_vector(63 downto 0));
end dec6to64;

Architecture Structure of dec6to64 is
component dec3to8
    port(
    w0,w1,w2, En : in std_logic;
    y0,y1, y2, y3, y4, y5, y6 ,y7 : out std_logic);
end component;


Begin
    process(w0, w1, w2, w3, w4, w5, En)
    Begin
        dec1: dec3to8 port map(w0, w1, w2, En, y0, y1, y2, y3, y4, y5, y6, y7);
        dec2: dec3to8 port map(w3, w4, w5, y0, f(0), f(1), f(2), f(3), f(4), f(5), f(6), f(7));
        dec3: dec3to8 port map(w3, w4, w5, y1, f(8), f(9), f(10), f(11), f(12), f(13), f(14), f(15));
        dec4: dec3to8 port map(w3, w4, w5, y2, f(16), f(17), f(18), f(19), f(20), f(21), f(22), f(23));
        dec5: dec3to8 port map(w3, w4, w5, y3, f(24), f(25), f(26), f(27), f(28), f(29), f(30), f(31));
        dec6: dec3to8 port map(w3, w4, w5, y4, f(32), f(33), f(34), f(35), f(36), f(37), f(38), f(39));
        dec7: dec3to8 port map(w3, w4, w5, y5, f(40), f(41), f(42), f(43), f(44), f(45), f(46), f(47));
        dec8: dec3to8 port map(w3, w4, w5, y6, f(48), f(49), f(50), f(51), f(52), f(53), f(54), f(55));
        dec9: dec3to8 port map(w3, w4, w5, y7, f(56), f(57), f(58), f(59), f(60), f(61), f(62), f(63));
    end process;
end Structure;

推荐答案

正如 Morten 指出的那样，实例化组件和组件声明之间存在端口接口列表不匹配.

As Morten pointed out there's a port interface list mismatch between the instantiated component and the component declaration.

这个分析:

library ieee;
use ieee.std_logic_1164.all;

entity dec6to64 is
end entity;

architecture foo of dec6to64 is
    signal w0,w1,w2, En: std_logic;
    signal  y0,y1, y2, y3, y4, y5, y6 ,y7: std_logic;
component dec3to8
    port(
    w0,w1,w2, En : in std_logic;
    y0,y1, y2, y3, y4, y5, y6 ,y7 : out std_logic);
end component;

begin
dec1: dec3to8 port map(w0, w1, w2, En, y0, y1, y2, y3, y4, y5, y6, y7);

end architecture;

y0 已添加到组件声明中.

y0 has been added to the component declaration.

以及您要分析的代码示例设置:

And your code sample setup to analyze:

    library ieee;
Use ieee.std_logic_1164.all;

entity dec6to64 is
    port (w0,w1,w2,w3,w4,w5, En : in std_logic;
            f : out std_logic_vector(63 downto 0));
end dec6to64;

Architecture Structure of dec6to64 is
        signal  y0,y1, y2, y3, y4, y5, y6 ,y7: std_logic; -- ADDED
component dec3to8
    port(
    w0,w1,w2, En : in std_logic;
    y0,y1, y2, y3, y4, y5, y6 ,y7 : out std_logic);
end component;


Begin
   --  process(w0, w1, w2, w3, w4, w5, En) component instantiations
    -- Begin                               are concurrent statements
        dec1: dec3to8 port map(w0, w1, w2, En, y0, y1, y2, y3, y4, y5, y6, y7);
        dec2: dec3to8 port map(w3, w4, w5, y0, f(0), f(1), f(2), f(3), f(4), f(5), f(6), f(7));
        dec3: dec3to8 port map(w3, w4, w5, y1, f(8), f(9), f(10), f(11), f(12), f(13), f(14), f(15));
        dec4: dec3to8 port map(w3, w4, w5, y2, f(16), f(17), f(18), f(19), f(20), f(21), f(22), f(23));
        dec5: dec3to8 port map(w3, w4, w5, y3, f(24), f(25), f(26), f(27), f(28), f(29), f(30), f(31));
        dec6: dec3to8 port map(w3, w4, w5, y4, f(32), f(33), f(34), f(35), f(36), f(37), f(38), f(39));
        dec7: dec3to8 port map(w3, w4, w5, y5, f(40), f(41), f(42), f(43), f(44), f(45), f(46), f(47));
        dec8: dec3to8 port map(w3, w4, w5, y6, f(48), f(49), f(50), f(51), f(52), f(53), f(54), f(55));
        dec9: dec3to8 port map(w3, w4, w5, y7, f(56), f(57), f(58), f(59), f(60), f(61), f(62), f(63));
   -- end process;
end Structure;

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