vhdl:赛灵思代码错误 [英] vhdl: Xilinx code error

问题描述

我们得到这个错误集:

Line 23: Mismatch in number of elements assigned in conditional signal assignment
Line 23: Expression has 1 elements ; expected 7

使用此代码，第 23 行是

With this code, line 23 is

Q_out <= "1111110" when Q_in = "0000" else


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder is
Port (
      Q_in  : in  UNSIGNED (3 downto 0);
      Q_out : out  UNSIGNED (6 downto 0)
);
end decoder;
architecture behavioral      of decoder is
begin
Q_out <= "1111110" when Q_in = "0000" else
        "0110000" when Q_in = "0001" else
        "1101101" when Q_in = "0010" else
        "1111001" when Q_in = "0011" else
        "0110011" when Q_in = "0100" else
        "1011011" when Q_in = "0101" else
        "0011111" when Q_in = "0110" else
        "1110000" when Q_in = "0111" else
        "1111111" when Q_in = "1000" else
        "1110011" when Q_in = "1001" else 
        "X";


 end behavioral    ;

推荐答案

VHDL 是强类型的，这意味着当您分配信号时，您需要匹配端口宽度和类型.在您的情况下，您没有匹配端口宽度，这就是错误告诉您的.您正在尝试将 1 位宽的内容分配给 7 位宽的内容.试试:

VHDL is strongly typed, meaning that when you assign signals you need to match port widths and types. In your case, you did not match port widths, which is what the error is telling you. You are trying to assign something that is 1 bit wide to something that is 7 bits wide. Try:

 "1110011" when Q_in = "1001" else 
 (others => 'X');

VHDL 中的 others 关键字意味着它将填充尽可能多的 X 以适当地匹配端口宽度.

The others keyword in VHDL means that it will fill up as many X's are needed to match port widths appropriately.

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