VHDL通用Fulladder代码 [英] Vhdl generic fulladder code

问题描述

这是级联全加器的通用代码.

问题是，fulladder的结果出现一个事件延迟(我的意思是，当我更改输入1和输入2时，将显示先前输入的结果).我知道，如果我在没有进程的情况下编写代码，则不会发生这种延迟，但是我需要编写一个通用的fulladder，并且没有办法在没有进程和for循环的情况下无法编写通用代码.

所以我要问是否有人可以帮助我修复代码，以便输出无延迟地显示结果！！！

  LIBRARY IEEE;使用IEEE.STD_LOGIC_1164.ALL;实体加法器为通用的(numberOfInputs:整数:= 4);港口(enable:在std_logic;中cin:在std_logic中；input1:在std_logic_vector(numberOfInputs-1降至0)中;input2:在std_logic_vector(numberOfInputs-1降至0)中;输出:输出std_logic_vector(numberOfInputs降至0));最终实体加法器；加法器的架构Generic_Adder是信号Couts:std_logic_vector(numberOfInputs降至0);信号temp1:std_logic_vector(numberOfInputs-1降至0);信号temp2:std_logic_vector(numberOfInputs-1降至0);信号temp3:std_logic_vector(numberOfInputs-1降至0);开始temp2< = inputs1;temp3< = inputs2;couts(0)< = cin;Sum:process(temp2，temp3，cin，enable，Couts)是开始用于在0到numberOfInputs-1循环中计数temp1(count)< =(temp2(count)x或temp3(count));输出(计数)< =出口(计数)x或temp1(计数);Couts(count + 1)< =(temp2(count)和temp3(count))或(couts(count)和temp1(count));-cout(count)是上一个cout，因为第一个cout是cin结束循环；结束过程；输出(numberOfInputs)< = Couts(numberOfInputs);结束Generic_Adder; 

解决方案

在此过程中使用了 temp1 信号，但灵敏度列表中未包含该信号.

temp1 中的更改将不会触发该过程的重新评估，并且 temp1 的新值不会在其他驱动信号中反映出来，直到另一个信号触发了重新评估，因此您可能会遇到延迟".

通过在敏感度列表中添加 temp1 来解决此问题，或者按照Bill Lynch的建议进行重写，或者如果您使用的是VHDL-2008和兼容的编译器，那么敏感度列表可以是 process(全部)... .

此外，由于在进程中循环驱动 outputs 和在驱动程序之外的 outputs(numberOfInputs)，因此会遇到与最长静态前缀"有关的VHDL问题.过程.结果是 outputs(numberOfInputs)在进程外具有一个驱动程序为'U'，在进程外具有一个驱动程序为 Couts(numberOfInputs).基于 std_logic 解析函数的结果值是'U'"值.

解决此问题的一种方法是在保留过程的同时，将 outputs(numberOfInputs)移动到过程内部，例如:

  ...结束循环；输出(numberOfInputs)< = Couts(numberOfInputs);结束过程； 

此答案 https://stackoverflow.com/a/18248941/2352082 具有有关VHDL最长静态前缀的更多信息

here is a generic code of a cascade full adder.

the problem is that the result of the fulladder appears with one event delay(I mean that when I change inputs1 & inputs2 the result of the previous inputs appears). I know that if I write the code without a process this delay wouldn't occur but I need to write a generic fulladder and there is no way to write a generic code without a process and a for loop.

so I'm asking if anyone could help me to fix the code so that the output would show the results with no delay!!!

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity adders is
    generic(
        numberOfInputs : Integer := 4
    ); port(
        enable  : in std_logic;
        cin     : in std_logic;
        inputs1 : in std_logic_vector(numberOfInputs-1 downto 0);
        inputs2 : in std_logic_vector(numberOfInputs-1 downto 0);
        outputs : out std_logic_vector(numberOfInputs downto 0)
    );
end entity adders;

architecture Generic_Adder of adders is
    signal Couts:std_logic_vector(numberOfInputs downto 0);
    signal temp1:std_logic_vector(numberOfInputs-1 downto 0);
    signal temp2:std_logic_vector(numberOfInputs-1 downto 0);
    signal temp3:std_logic_vector(numberOfInputs-1 downto 0);

begin

    temp2<=inputs1;
    temp3<=inputs2;  
    couts(0)<= cin;

    Sum:process(temp2,temp3,cin,enable,Couts) is
    begin
        for count in 0 to numberOfInputs-1 loop
            temp1(count) <= (temp2(count) xor temp3(count));
            outputs(count) <= Couts(count) xor temp1(count);
            Couts(count+1) <= (temp2(count) and temp3(count)) or(couts(count) and temp1(count));--cout(count) is the previuos cout becuase the first cout is cin
        end loop;
    end process;

    outputs(numberOfInputs) <= Couts(numberOfInputs);
end Generic_Adder;

解决方案

The temp1 signal is used in the process, but it is missing in the sensitivity list.

Changes in temp1 will therefore not trigger reevaluation of the process, and the a new value of temp1 is not reflected in other driven signals until another signal trigger reevaluation, hence you are likely to experience a "delay".

Fix this by adding temp1 to the sensitivity list, or rewrite as suggested by Bill Lynch or if you are using VHDL-2008 and compatible compiler, then the sensitivity list can be process (all) ....

In addition, a VHDL issue related to "longest static prefix" is encountered due to the drive of outputs by loop in the process and outputs(numberOfInputs) outside the process. The result is that outputs(numberOfInputs) has a driver as 'U' from the process and a driver as Couts(numberOfInputs) outside the process. The resulting value, based on the std_logic resolution function, is a value of ´'U'´.

One way to fix this issue, when keeping the process, is to move the outputs(numberOfInputs) inside the process, like:

        ...
    end loop;
    outputs(numberOfInputs) <= Couts(numberOfInputs);
end process;

This answer https://stackoverflow.com/a/18248941/2352082 has more information about VHDL longest static prefix.

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