是否可以用VHDL编写类型通用实体？ [英] Is it possible to write type-generic entities in VHDL?

问题描述

所以，我最近继承了一些VHDL代码，我的第一反应是，VHDL有结构，为什么他们在任何地方都使用位向量？然后我意识到这是因为似乎没有任何方法来写这样的东西：

 实体队列是
通用（
 EL：类型
）; 
端口（
 data_in：EL; 
 data_out：EL; 
 ... 
）; 
结束实体队列; 
  

我真的希望这是可能的。有什么东西甚至可以远程接近它？即使我不得不重新输入实体或组件声明，只需要一些方法来避免重新输入每个（模通用宽度）类型的体系结构定义？ 解决方案

是的，并且实现Queue是这样做的经典理由之一！

自VHDL-2008开始，这就是VHDL。工具支持在2012年年中是变化的。谈论一个缓慢发展的行业！

• Aldec 完全支持。


• Modelsim部分支持 - 无法找到公开链接。如果安装了它，它位于/technotes/vhdl2008.note


• 赛灵思（XST / ISIM）不支持它，甚至不支持VHDL-2002。我无法找到简单的链接，但这些 PDFs 有关于VHDL兼容性的部分，这些部分仅涉及VHDL-1993。
  
• Altera的工具有部分支持，但不适用于类型泛型

So, I recently inherited some VHDL code, and my first reaction was, "VHDL has structs, why do they use bit-vectors everywhere?" And then I realized this is because there does not seem to be any way to write anything like this:

entity Queue is
    generic (
        EL : type
    );
    port (
        data_in  : EL;
        data_out : EL;
        ...
    );
end entity Queue;

I really wish this were possible. Is there anything even remotely approximating it? Even if I have to retype the entity or component declarations, just some way to avoid retyping the architecture definition for every (modulo a generic width) type?

解决方案

Yes, and implementing a Queue is one of the classic reasons to do it!

This has been in VHDL since VHDL-2008. Tool support is variable as of mid-2012. Talk about a slow-moving industry!

• Aldec supports it completely.
• Modelsim has partial support - can't find a public link to their capabilities. If you have it installed, it's in /technotes/vhdl2008.note
• Xilinx (XST/ISIM) doesn't support it, or even VHDL-2002. I can't find a simple link, but these PDFs have sections on VHDL compatibility, which only talk of VHDL-1993.
• Altera's tools have partial support, but not for type generics

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