通用记录(通过 vhdl 2008 通用包尝试) [英] Generic Records (attempted via vhdl 2008 generic package)

问题描述

我想为组件C写一个库，组件内部拆分成两个supcomponentsc1和c2，可以通过仿制药.子模块应该通过一个记录连接，这取决于泛型.该记录也应在组件内使用.通常我会在 package 中实例化记录，并在子组件的文件和组件的文件中使用该包.由于它是通用的，我认为使用通用包 (VHDL-2008) 可能会提供一个解决方案.

I want to write a library for component C, the component is split internally into two supcomponents c1 and c2, which are configurable by generics. The submodules should be connected by a record, that depends on the generics. The record should also be used within the components. Usually I would instantiate the record in a package, and use the package in the files for the subcomponents and in the file for the component. Since it is generic I figured using a generic Package (VHDL-2008) might offer a solution.

问题是我还需要从子组件中访问记录.为此，我需要使用 thePackage，但是要使用通用包，我需要传递初始值(据我所知).

The Problem is I need to access the record also from within the subcomponents. To do so I need to use thePackage, however to use a generic package I need to pass initial values (as far as I know).

所以我尝试了(注意:我不是在这里处理记录，我只是想从通用组件访问通用包，在那里我用组件的参数参数化(?)包):

So I tried (note: Iam not working with records here, I am just trying to get access to a generic package from a generic component, where I parameterize(?) the package with the parameters of the component):

entity genericPackagePart is
    generic(
        outputValue : integer
    );
    port(
        result: out integer
    );
end entity;

architecture behav of genericPackagePart is
    package test is new work.genericPackage
    generic map(
        genSize => outputValue
    );

    use work.test.all;
begin
    result <= dummy;  -- dummy is a constant from genericPackage set to the value genSize (generic parameter)
end architecture;

但是我从modelsim得到以下错误:

However I get the following errors from modelsim:

** Error: (vcom-11) Could not find work.test.
** Error: genericPackagePart.vhd(17): (vcom-1195) Cannot find expanded name "work.test".
** Error: genericPackagePart.vhd(17): Unknown expanded name.
** Error: genericPackagePart.vhd(19): (vcom-1136) Unknown identifier "dummy".
** Error: genericPackagePart.vhd(20): VHDL Compiler exiting

更新:我尝试将 genericPackagePart 包装在一个通用包中，并使用泛型从该包中实例化 genericPackage ，这也不起作用.

Update: I tried wrapping the genericPackagePart in a generic package and to instantiate the genericPackage from within that package with the generics, this did not work either.

流程应该是:

• Testbench => 使用通用参数实例化 genericPackagePart 和 genericPackage
• 该记录在 genericPackage 的测试平台中可用
• Inside genericPackagePart genericPackage 使用传递给 genericPackagePart
的参数实例化
• 记录在 genericPackagePart
中可用

• Testbench => Instantiate genericPackagePart and genericPackage with generic parameters
• The record is available in the testbench from genericPackage
• Inside genericPackagePart genericPackage is instantiated with the parameters passed to genericPackagePart
• the record is available inside genericPackagePart

Modelsim 给出了错误(test 是我给genericPackagePart 中genericPackage 的参数化实例起的名字，这是来自genericPackagePart 的编译代码>genericPackagePart):

Modelsim gave Errors (test is the name I gave to the parameterizes instance of genericPackage in genericPackagePart, this is from the compile of genericPackagePart):

** Error: (vcom-11) Could not find work.test.
** Error: genericPackagePart.vhd(11): (vcom-1195) Cannot find expanded name "work.test".
** Error: genericPackagePart.vhd(11): Unknown expanded name.
** Error: genericPackagePart.vhd(13): near "entity": expecting END

<小时>

我查看了将泛型传递给记录端口类型，但这并没有解决基于泛型的包实例化问题

---

I looked at Passing Generics to Record Port Types but that does not solve the issue of the package instantiation based on generics

为了完整起见，这里是包和测试平台:

For completness here is the package and a testbench:

包装:

package genericPackage is
    generic(genSize : integer := 1);

    constant dummy : integer := genSize;
end package;

测试平台:

package myGenericPackage is new work.genericPackage
generic map(
    genSize => 5
);

use work.myGenericPackage.all;

entity genericPackageTestbench is
end entity;

architecture testbench of genericPackageTestbench is
    signal testsignal : integer;
    signal testsignal2 : integer;
    signal dummy : integer := 12;

    component genericPackagePart is
    generic(
        outputValue : integer
    );
    port(
        result: out integer
    );
    end component;
begin
    test : process is
    begin
        wait for 20 ns;
        testsignal <= dummy;
        wait for 20 ns;
        testsignal <= work.myGenericPackage.dummy;
        wait;
    end process;

    testPart: genericPackagePart
        port map(result => testsignal2)
        generic map(outputValue => 128);
end architecture;

推荐答案

我认为问题是你的包 test 需要定义在实体区，而不是架构区:

I think the problem was that your package test needs to be defined in the entity area, not the architecture area:

package genericPackage is
    generic(genSize : integer := 1);
    constant dummy : integer := genSize;
end package;
entity genericPackagePart is
    generic(outputValue : integer);
    port(result : out integer);

    -- *** Generic package instantiated here ***
    package test is new work.genericPackage
       generic map(genSize => outputValue);

end entity;
architecture behav of genericPackagePart is
    use test.all;
begin
    result <= dummy;  -- dummy is from genericPackage (=genSize)
end architecture;

这是我测试它的方式(基于您的测试平台):

Here's how I tested it (based on your testbench):

package myGenericPackage is new work.genericPackage
   generic map(genSize => 5);

use work.myGenericPackage.all;

entity genericPackageTestbench is
end entity;

architecture testbench of genericPackageTestbench is
    signal testsignal  : integer;
    signal testsignal2 : integer;
begin
    test : process is
    begin
        testsignal <= work.myGenericPackage.dummy;
        wait for 20 ns;

        assert testsignal = work.myGenericPackage.dummy 
            report "test signal should be work.myGenericPackage.dummy" 
            severity error;
        assert testsignal2 = 128 report "testsignal2 /= 128" severity error;
        report "testsignal = " & integer'image(testsignal);
        report "testsignal2 = " & integer'image(testsignal2);
        report "Finished";
        wait;
    end process;

    testPart : entity work.genericPackagePart
        generic map(outputValue => 128)
        port map(result         => testsignal2);
end architecture;

使用 Modelsim 10.2 编译和仿真:

Compiled and simulated with Modelsim 10.2:

vcom -2008 genpacktest.vhd; vsim -c genericPackageTestbench -do "run -all; quit"

哪些报告:

# Loading std.standard
# Loading work.genericpackage
# Loading work.mygenericpackage
# Loading work.genericpackagetestbench(testbench)
# Loading work.genericpackagepart(behav)
# run -all 
# ** Note: Finished
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
# ** Note: testsignal = 5
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
# ** Note: testsignal2 = 128
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
#  quit 

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