具有通用数据宽度VHDL的多维存储器 [英] Multidimensional memory with generic data width VHDL

问题描述

我想知道如何声明一个具有通用数据宽度的二维内存

  package mem_pkg is 
子类型数据是std_logic_vector（7 downto 0）; 
 type data_vector是数据的数组（自然范围） 
 end; 
实体mem是
端口（
 clk：在std_logic中; 
我们：在std_logic中 - 写入启用
a：在unsigned（4 downto 0）中;  - 地址
 di：in data;  -  data_in 
 do：out data  -  data_out 
）; 
 end mem; 
  

---

而不是7，我希望数据宽度为是不通用的。

解决方案

这不是二维的 - 这是一个矢量矢量，它是（微妙）不同的。

二维数组是

  type data_vector是数组（自然范围<> ，自然范围>）; 
  

但是，回到您的问题：

直到最近（VHDL 2008），你不可能拥有一个无约束数组的无约束数组。但现在你可以这样做：

  type mem是std_logic_vector的数组（自然范围<>）; 
信号存储：mem（0到15）（7 downto 0）; 
  

VHDL 2008 - 只是新东西有更多细节：

http：// books.google.co.uk/books?id=ETxLguPMEY0C&lpg=PA241&ots=q7u_Mn0SFR&dq=vhdl%202008%20just%20the%20new%20stuff%20p%20120&pg=PA120#v=snippet&q=别名％20％％20a％20register％20file％20signal& f = false

I would like to know how to declare a 2-dimensional memory with a generic data width

package mem_pkg is
  subtype data is std_logic_vector(7 downto 0);
  type data_vector is array( natural range <> ) of data;
end;
entity mem is
port (
  clk : in std_logic;
  we : in std_logic -- write enable
  a: in unsigned(4 downto 0); -- address
  di : in data; -- data_in
  do : out data -- data_out
 );
 end mem;

---

Instead of 7, I want the data width to be generic.

解决方案

That's not two dimensional - that's a vector of vectors, which is (subtly) different.

A 2D array is

type data_vector is array (natural range <>, natural range <>) of integer;

But, back to your problem:

Until "recently" (VHDL 2008) you couldn't have an unconstrained array of an unconstrained array. But now you can do:

type mem is array(natural range <>) of std_logic_vector;
signal store : mem(0 to 15)(7 downto 0);

"VHDL 2008 - just the new stuff" has much more detail:

http://books.google.co.uk/books?id=ETxLguPMEY0C&lpg=PA241&ots=q7u_Mn0SFR&dq=vhdl%202008%20just%20the%20new%20stuff%20p%20120&pg=PA120#v=snippet&q=alias%20of%20a%20register%20file%20signal&f=false

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