VHDL中的灵活/通用解码器的想法 [英] Ideas for a flexible/generic decoder in VHDL

问题描述

我想创建一个地址解码器，该地址解码器足够灵活，可以在更改选择器和解码后的输出信号的位数时使用.

I want to create an address Decoder that is flexible enough for me to use when changing the number of bits of the selector and of the decoded output signals.

因此，与其使用静态(固定的输入/输出大小)解码器，而不是像这样:

So, instead of having a static (fixed input/output size) Decoder that looks something like this :

entity Address_Decoder is
Generic
(
    C_INPUT_SIZE: integer := 2
);
Port
(
    input   : in  STD_LOGIC_VECTOR (C_INPUT_SIZE-1 downto 0);
    output  : out STD_LOGIC_VECTOR ((2**C_INPUT_SIZE)-1 downto 0);
    clk : in  STD_LOGIC;
    rst : in  STD_LOGIC
);
end Address_Decoder;

architecture Behavioral of Address_Decoder is

begin        
        process(clk)
            begin
               if rising_edge(clk) then 
                  if (rst = '1') then
                     output <= "0000";
                  else
                     case <input> is
                        when "00" => <output> <= "0001";
                        when "01" => <output> <= "0010";
                        when "10" => <output> <= "0100";
                        when "11" => <output> <= "1000";
                        when others => <output> <= "0000";
                     end case;
                  end if;
               end if;
            end process;

end Behavioral;

具有一些更灵活/更通用的内容，如下所示:

Have something that is more flexible/general, that looks like this:

    entity Address_Decoder is
    Generic
    (
        C_INPUT_SIZE: integer := 2
    );
    Port
    (
        input   : in  STD_LOGIC_VECTOR (C_INPUT_SIZE-1 downto 0);
        output  : out STD_LOGIC_VECTOR ((2**C_INPUT_SIZE)-1 downto 0);
        clk : in  STD_LOGIC;
        rst : in  STD_LOGIC
    );
    end Address_Decoder;

    architecture Behavioral of Address_Decoder is

    begin        

DECODE_PROC:
    process (clk)
    begin

        if(rising_edge(clk)) then
         if ( rst = '1') then
           output <= conv_std_logic_vector(0, output'length);
         else
           case (input) is
             for i in 0 to (2**C_INPUT_SIZE)-1 generate
             begin
                when (i = conv_integer(input)) => output <= conv_std_logic_vector((i*2), output'length);        
             end generate;
            when others => output <= conv_std_logic_vector(0, output'length);
           end case;
         end if;
        end if;
    end process;

    end Behavioral;

我知道这段代码是无效的，并且何时"测试用例必须是常量，并且我不能在这样的case语句之间使用for-generate，但是它表明了我所追求的是:一个足够聪明的实体可以满足我的需求.

I know this code is not valid and that the "when" test cases must be constants and that I can't use the for-generate in between the case statement like that, but it shows what it is that I am after: an entity smart enough to grow to my needs.

我一直试图为该问题找到一个好的解决方案，但是收效甚微，因此，我愿意提出任何建议.

I have been trying to find an elegant solution for this problem without much success, so, I'm open for any suggestions.

预先感谢， 埃里克

推荐答案

显然，您希望输入是应该设置的输出位的索引.

Apparently you want the input to be the index of the output bit that should be set.

这样写.诸如此类(假设来自numeric_std的类型):

Write it like that. Something like (assuming types from numeric_std):

output <= (others => '0'); -- default
output(to_integer(input)) <= '1';

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