VHDL中的语法错误 [英] Syntax error in VHDL
问题描述
我正在尝试使用结构化的VHDL和组件来实现一位计数器。
尝试做端口映射时出现语法错误。
错误是错误(10028):在Assign4.vhd(47)处无法解析网络 P的多个常量驱动程序
这是我到目前为止所拥有的:
谢谢
I am trying to implement a one bit counter using structural VHDL and components. I am getting a syntax error when trying to do the port map. The error is "Error (10028): Can't resolve multiple constant drivers for net "P" at Assign4.vhd(47)" Here is what I have so far: Thank you in advance for any ideas.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------
Entity Assign4 is
Generic (bits: POSITIVE := 1);
Port (CLK: in std_logic;
SE1,SE2: in std_logic;
P: out std_logic);
End Entity Assign4;
---------------------------------------------------------------
Architecture Structural of Assign4 is
--------------------------------
Component Counter is
-- Generic (N: Positive := 1);
Port(clock,sel1,sel2: in std_logic;
Q: out std_logic);
End Component;
--------------------------------
Signal x,y,z: std_logic;
begin
P <= x;
--Qn <= x;
process(CLK)
begin
if (Clk'event and CLK = '1') then
x <= x xor (SE1 and SE2);
end if;
end process;
--------------COUNTER-------------------------------------
count1: Counter PORT MAP (clk,SE1,SE2,P);
---------------END COUNTER--------------------------------
-- The generate will be used later for implementing more bits in the counter
--gen: FOR i IN 0 TO 1 GENERATE
-- count1: Counter PORT MAP (SE1 <= inbits(0),SE2 <= inbits(1),clock <= CLK,
-- outA <= SE1 and SE2, q <= outA xor q);
--end GENERATE gen;
---------------------------------------------------
end Architecture;
推荐答案
错误消息很不言自明:您是从两个不同的地方驾驶P:
The error message is fairly self-explanatory: you are driving P from two different places:
P <= x;
和
count1: Counter PORT MAP (clk, SE1, SE2, P);
(在计数器组件中,您已将最后一个端口列为输出,因此它正在驱动
(In the Counter component, you've listed the last port as an output, so it is driving P also.)
虽然可能是后者,但我无法说出您想要哪条语句。您将要注释掉第一次分配,这将解决此编译错误。
I cannot say which statement you want, though likely it is the latter; you'll want to comment out the first assignment, which will resolve this compilation error.
这篇关于VHDL中的语法错误的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!