VHDL 语法错误接近 if [英] VHDL syntaxe error near if

问题描述

我正试图通过这个简单的 VHDL 代码找出问题所在.如果有人可以帮助我，我将不胜感激.PS:我尝试了没有条件块的代码，它有效:S！

I'm a trying to find out the problem with this simple VHDL code. I'll be grateful if someone could help me. PS: I tried the code without the conditional block and it works :S !

*消息错误是:Error (10500): VHDL syntax error at Four_Bits_Adder.vhd(18) near text "if";期待;"，或标识符(if"是保留关键字)，或架构"*

*The message error is : Error (10500): VHDL syntax error at Four_Bits_Adder.vhd(18) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"*

4 位加法器代码是:

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;

entity Four_Bits_Adder is 
port(A,B:in std_logic_vector(3 downto 0);
    S:out std_logic_vector(3 downto 0);
    Cout:out std_logic);
end Four_Bits_Adder;
architecture description of Four_Bits_Adder is 
begin 
S<= A+B;
if A(3)=1 then 
    if B(3)=1 then 
        Cout<=1;
        end if;
end if;     
end description;

推荐答案

if 语句是一个顺序语句，从你的用法来看，应该要么在一个进程语句中，要么你应该使用并发信号赋值语句.对于流程语句来说，它似乎不够复杂.

An if statement is a sequential statement, and from your usage should either be in a process statement or you should instead use a concurrent signal assignment statement. It hardly seems complex enough for a process statement.

并发赋值语句:

 Cout <= A(3) and B(3);

请注意，使用表达式作为信号赋值中的值的并发赋值语句可以传递除0"或1"以外的值.

Note that concurrent assignment statement using an expression as the value in it's signal assignment can pass values other than '0' or '1'.

一种不同风格的并发信号赋值语句只能传递表示枚举值的二进制:

A different style of concurrent signal assignment statement could pass only binary representing enumeration values:

Cout <= '1'  when A(3) = '1' and B(3) = '1' else '0';

(您的 if 语句似乎也推断出一个闩锁，并且可以优化为常量1").

(Your if statement also appears to infer a latch and could be optimized as a constant '1').

还要注意，您原来的 if 嵌套语句可以用 BOOLEAN and 表示，它是一个短路运算符，代替了 Ada 的 if 表达式和然后....if 语句(包括它的 end if)后面没有一个或多个中间语句，就没有理由将 if 语句嵌套在不同的表达式中.如果第一个表达式的计算结果为真，则短路运算符只会计算随后的表达式.

Note also that your original if nested statements could be expressed with a BOOLEAN and which is a short-circuit operator taking the place of Ada's if expression and then .... Without one or more intervening statements following an if statement (including it's end if) there is no reason to nest if statements with different expressions. The short-circuit operator would only evaluate the subsequent expression if the first expression evaluated true.

表格应该是

if A(3) = '1' and B(3) = '1' then
    Cout <= '1';
end if;

并且仍然只能在适合顺序语句的情况下使用.

And could still only be used where a sequential statement is appropriate.

请注意，std_logic 需要枚举值('U'、'X'、'0'、'1'...)，而 1 是一个数值，会导致错误.

Note that std_logic requires enumeration values ('U', 'X', '0', '1',...) while 1 is a numeric value and would result in errors.

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