反转 VHDL 上的位顺序 [英] Reverse bit order on VHDL
本文介绍了反转 VHDL 上的位顺序的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!
问题描述
我在做类似的事情时遇到问题
I'm having trouble doing something like
b(0 to 7) <= a(7 downto 0)
当我用 ghdl 编译它时,出现顺序错误.我发现使我的电路工作的唯一方法如下:
when I compile it with ghdl, I have an order error. The only way I have found to make my circuit work is the following:
library ieee;
use ieee.std_logic_1164.all;
entity reverser is
port(
a: in std_logic_vector(7 downto 0);
y: out std_logic_vector(7 downto 0);
rev: in std_logic
);
end reverser;
architecture rtl of reverser is
signal b: std_logic_vector (7 downto 0);
begin
b(7) <= a(0);
b(6) <= a(1);
b(5) <= a(2);
b(4) <= a(3);
b(3) <= a(4);
b(2) <= a(5);
b(1) <= a(6);
b(0) <= a(7);
y <= b when rev = '1' else a;
end rtl;
建议?提前致谢
推荐答案
这是不允许的 - VHDL 是强类型的,如果你想反转位顺序,你必须明确地这样做.
That's not allowed - VHDL is so strongly typed that if you want to reverse bit orders, you have to do it explicitly.
标准的解决方案是使用函数(我没有写这个 - 乔纳森·布罗姆利做了):
The standard solution is to use a function (I didn't write this - Jonathan Bromley did):
function reverse_any_vector (a: in std_logic_vector)
return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end; -- function reverse_any_vector
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