VHDL 中的并发和顺序语句 [英] concurrent and sequential statements in VHDL

问题描述

我有一个关于 VHDL 的基本问题.

I have a fundamental question on VHDL.

考虑以下过程:

process(Clk)
begin
if(rising_edge(Clk)) then
  a <= data_in;
  b <= a;
  c <= b;
  data_out <= c;
end if;
end process;

以上过程起到了延迟寄存器的作用，其中data_in在4个时钟周期后输出到data_out.

The above process acts as a delay register, where data_in is output to data_out after 4 clock cycles.

据我所知，这是因为信号是并行分配的.但是，为什么一个过程中的语句称为顺序?

From my understanding this happens because signals are assigned parallelly. But then why does the statements inside a process called sequential?

例如:

process(Clk)
begin
if(rising_edge(Clk)) then
  a <= b or c;
  a <= b and c;
end if;
end process;

在上面的过程中，a"从第二个语句中获取值，我理解它与第一个过程不同，它是如何以顺序方式工作的.

In the above process the 'a' takes the value from the 2nd statement and I understand, how it works in a sequential way unlike the first process.

请帮忙.

推荐答案

其实很简单:VHDL 进程中的所有语句都是按顺序执行的，从上到下，没有例外.然而，

It's actually very simple: all statements inside a VHDL process are executed sequentially, in order, from top to bottom, no exceptions. However,

1. 信号赋值运算符(<=)的左侧没有取其新值，直到进程(和所有其他进程)具有暂停(要么触底，要么触发等待语句)和

1. the left hand side of a signal assignment operator (<=) does not take its new value until the process (and all other processes) have suspended (either hit the bottom or hit a wait statement) and

如果你再次分配给一个信号(如你的第二个例子)最后一个执行的赋值覆盖了之前的赋值.

if you assign to a signal again (as in your second example) the last assignment executed overwrites the previous ones.

现在你知道了，在你的脑海中模拟上述两个过程，你会看到它们的行为就像你说的那样.(第一个示例中的语句不是并行执行的.但由于上面的(1)，它们似乎是.)

Now you know that, simulate the above two processes in your head and you will see that they behave as you say they will. (The statements in your first example are NOT executed in parallel. But because of (1) above, it seems like they are.)

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