vhdl 中的进程语句 [英] process statement in vhdl

问题描述

我正在尝试学习 VHDL 并努力学习它的一些基础知识.问题如下:

I am trying to learn VHDL and struggling with some of its basics. The question is as follows:

Process 语句被描述为包含顺序运行的代码(一行一行).我想问一下为什么不能在 process 语句中运行并发代码(意味着所有行并行执行).其次，如果过程语句包含顺序代码，它如何建模，例如，三个触发器并发，例如，

Process statement is described to contain code that runs sequentially (one line after the other). I want to ask why can't one run concurrent code in a process statement (means all lines execute in parallel). Secondly, if process statement contains sequential code, how can it model for example, three flip-flops concurrently e.g.,

--内部流程声明

Q1 <= D1;
Q2 <= Q1;
Q3 <= Q2;

推荐答案

顺序与评估语句的顺序有关，而不是在赋值生效时.

Sequential relates to the order the statements are evaluated, not when the assignment takes effect.

VHDL 仿真周期

信号分配不会立即生效，它们被安排在当前或未来的时间，并且在分配生效之前完成当前模拟周期中对信号事务敏感的所有进程.(在 VHDL 中，一切都转化为等效的块层次结构、流程和用于仿真的函数调用.)

Signal assignments don't take effect immediately, they are scheduled for the current or a future time and all processes sensitive to signal transactions in the current simulation cycle being are completed before the assignments take effect. (And in VHDL everything devolves into equivalent block hierarchy, processes and function calls for simulation.)

当所有当前活动的进程完成模拟时间前进到下一次信号在任何信号投影输出波形(队列)中处于活动状态时，除非当前模拟时间有事件，在这种情况下，我们将下一个模拟周期称为增量周期.

When all currently active processes complete simulation time advances to the next time a signal is active in any signal projected output waveform (a queue) unless there are events at the current simulation time, in which case we call the next simulation cycle a delta cycle.

执行对信号事务敏感的每个进程，并将任何进一步的信号分配给相应的投影输出波形.每个信号的当前仿真时间队列中只有一个槽".

Each process that is sensitive to a signal's transactions is executed and any further signal assignments are made to the respective projected output waveform. There is only one 'slot' in the queue for the current simulation time for each signal.

这样就没有任何进程击中移动目标.一次只执行一个进程，直到所有进程都执行完毕后，信号分配才会生效.这模拟了并发，当包含顺序语句的进程按顺序执行时模拟并行执行.

In this way there aren't any processes hitting moving targets. Only one process executes at a time, no signal assignments take effect until all processes have completed execution. This emulates concurrency, mimicking parallel execution when processes containing sequential statements are executed sequentially.

Q1 <= D1; 等赋值相当于 Q1 <= D1 after 0 ns; 表示当前的仿真时间.如果过程中的一系列顺序语句在当前仿真时间包含对同一信号的后续赋值，并且赋值不同，则第二个赋值将替换投影输出波形中的第一个赋值.

An assignment such as Q1 <= D1; is equivalent to Q1 <= D1 after 0 ns; meaning the current simulation time. If a series of sequential statements in a process contain a subsequent assignment to the same signal at the current simulation time and the assigned value is different the second assignment will replaced the first one in the projected output waveform.

当当前仿真时间没有为信号安排更多事件时，仿真时间将提前到任何提前仿真时间的预测输出波形队列中任何事务时间的最早时间.

When there are no more events scheduled for signals at the current simulation time, simulation time will advance to the earliest time of any transaction time in any projected output waveform queue advancing simulation time.

当没有其他队列事件时，模拟时间将提前到 Time'HIGH(可能的最高模拟时间)并停止模拟.

When there are no further queue events simulation time will advance to Time'HIGH (the highest possible simulation time) and simulation will cease.

还可以通过控制允许模拟运行多长时间的实现或通过执行严重级别为 FAILURE 或实现定义的用于停止模拟的严重级别阈值的断言语句来停止模拟.

Also simulation can be stopped by an implementation controlling how long to allow the simulation to run or by execution of an assertion statement with a SEVERITY LEVEL of FAILURE or an implementation defined severity level threshold for stopping simulation.

这篇关于vhdl 中的进程语句的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！