如何避免VHDL中简单流程语句的输出延迟 [英] how to avoid delay in the output of simple process statement in VHDL

问题描述

我是 VHDL 的初学者.我想知道为什么在下面的代码中有一个周期的延迟.以及如何避免它.同时在 verilog 中，语句总是 @(posedge clk) 没有任何延迟 .. 如何在 verilog 中做同样的事情VHDL

i am a beginner in VHDL. i want ot know why there is a delay of one cycle in the following code.and how to avoid it..at the same time in verilog the statement always @(posedge clk) dont have any delay.. how to do the same in VHDL

library IEEE;
 use IEEE.std_logic_1164.all;

   -- entity
entity t_ff_s is
port ( T,S,CLK : in std_logic;
Q : out std_logic);
 end t_ff_s;
 -- entity
 architecture my_t_ff_s of t_ff_s is
signal t_tmp : std_logic; -- intermediate signal declaration
  begin
    tff: process (S,rising_edge(clk))
     begin
        if (S = '0') then
     t_tmp <= '1';
      --elsif (rising_edge(CLK)) then
     else 
     t_tmp <= T XOR t_tmp; -- temp output assignment
     end if;
    end process tff;
     Q <= t_tmp; -- final output assignment
     end my_t_ff_s;

推荐答案

VHDL 中的灵敏度列表不像 Verilog 那样采用边缘规范.VHDL 更灵活，因为您可以在进程内的任何位置自由使用 'event 信号属性来实现边缘触发行为.您可以混合电平和边缘敏感逻辑，而无需诉诸分割块/进程或像 negedge 之类的 hack 来重置.在敏感度列表中不允许像 rising_edge(clk)(它实现对 clk'event 的测试)这样的函数调用.它只包含信号名称.您的代码不会按原样编译.

Sensitivity lists in VHDL don't take an edge specification like in Verilog. VHDL is more flexible in that you can freely use the 'event signal attribute anywhere within a process to implement edge triggered behavior. You can mix level and edge sensitive logic without resorting to split blocks/processes or hacks like negedge for resets. Function calls like rising_edge(clk) (which implements a test for clk'event) are not permitted in a sensitivity list. It only contains signal names. Your code won't compile as is.

如果您的代码的其他一些语法正确的版本可以干净利落地编译，那么您看到的延迟是模拟模型的伪影或敏感度列表损坏.如果你想要一个同步时钟驱动的过程，那么你只需要时钟信号和敏感列表中可能的异步复位.

If some other syntactically correct version of your code compiles cleanly, the delays you see are artifacts of the simulation model or having a broken sensitivity list. If you want a synchronous clock driven process then you only need the clock signal and possibly an asynchronous reset in the sensitivity list.

考虑以下过程:

tff: process(S, clk)
begin
  if S = '0' then -- Asynchronous reset (level sensitive)
    t_tmp <= '1';
  elsif rising_edge(clk) then -- Synchronous logic (edge sensitive)
    t_tmp <= T xor t_tmp;
  end if;
end process;

Q <= t_tmp;

这个过程在S 或clk 上发生事件时执行.如果 S 为0"，则重置条件的执行优先于 elsif 子句(clk 是无关紧要的).对 t_tmp 的分配在下一个增量周期生效，该周期仍与当前仿真时间相同.否则，如果 rising_edge(clk) 的计算结果为真，则 clk 上发生了一个事件，并且它的状态从0"(或L")变为1"(或'H') 表示事件是上升沿.同步赋值发生，新的异或 t_tmp 在下一个增量周期生效.T 中的更改不会导致进程执行，因为它不在(也不应该)在敏感列表中.

This process executes when an event occurs on S or clk. If S is '0' then the reset condition is executed with priority over the elsif clause (clk is a don't-care). The assignment to t_tmp takes effect on the next delta cycle which is still the same as the current simulation time. Otherwise, if rising_edge(clk) evaluates to true then an event occurred on clk and it's state changed from '0' (or 'L') to '1' (or 'H') indicating that the event was a rising edge. The synchronous assignment takes place and the new xored t_tmp takes effect on the next delta cycle. Changes in T don't cause the process to execute since it isn't (and shouldn't be) in the sensitivity list.

因为没有无条件的 else 子句，如果两个 if 条件都为假，t_tmp 信号将保留其最后分配的值.下次 S 或 clk 上的事件导致对 t_tmp 的新分配时，它将发生变化.这将是下一个时钟沿或异步复位的重新应用.

Because there is no unconditional else clause the t_tmp signal retains its last assigned value if both of the two if conditions are false. It will change the next time there is an event on S or clk that causes a new assignment to t_tmp. This will either be the next clock edge or a re-application of asynchronous reset.

对Q 的赋值是连续的，实际上与敏感列表中带有t_tmp 的进程相同.因此，对 Q 的分配发生在 t_tmp 事件之后的一个增量周期，这是上升沿之后的两个增量周期.如果 Q 输入的逻辑比边沿的第二个增量周期更早更新，它似乎需要额外的时钟周期才能传播.

The assignment to Q is continuous and is effectively the same as a process with t_tmp in its sensitivity list. As a consequence, the assignment to Q takes place a delta cycle after events on t_tmp which is two delta cycles after the rising edge. If Q is feeding into logic that updates earlier than the second delta cycle of an edge, it will appear to take an extra clock cycle for it to propagate.

在检查波形时，围绕增量周期的行为有时会产生令人困惑的结果.您可能有一个上升沿，它应该捕获似乎在同一时间步同时转换的数据输入，而实际上，数据正在稍后的增量周期中转换，并且只会在下一个时钟沿.

The behavior surrounding delta cycles can sometimes create confusing results when inspecting waveforms. You may have a rising edge that should capture a data input that appears to transition simultaneously on the same time step when, in fact, the data is transitioning on a later delta cycle and will only be captured on the next clock edge.

同样，如果您构建一个没有任何时间延迟的简单门控时钟，它的边沿将同时出现，但会出现在比非门控时钟版本晚的增量周期.因此，门控逻辑将从较早的"非门控时钟驱动的数据比预期早一个时钟周期捕获.另一个方向驱动的数据会出现一个时钟周期的意外延迟.

Similarly, if you construct a simple gated clock without any time delay, its edges will occur at the same time but on later delta cycles than the ungated version of the clock. Data driven from the "earlier" ungated clock will be captured by the gated logic a clock cycle earlier than expected as a result. Data driven the other direction will appear to have an unexpected delay by a clock cycle.

如果没有更多关于如何驱动 S、T 和 clk 信号，但它可能以某种方式与仿真引擎的增量循环行为相关联.

It isn't clear what is causing the problem you see without more information on how you're driving the S, T, and clk signals but it is likely connected to the delta cycle behavior of the simulation engine in some way.

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