VHDL：无法读取输出状态 [英] VHDL: Unable to read output status

问题描述

我正在尝试在ModelSim 10.0中进行编译，但收到一个编译错误，指出：
'无法读取输出状态'。

I'm attempting to compile in ModelSim 10.0 and I receive a compile error stating: 'Cannot read output status'.

以下是代码。

entity controller_entity is
generic( entryCount : positive := 2;
         ....);
port(
    clk         : in  std_logic;
    ....
    entry_car_entered : out std_logic_vector(0 to entryCount-1)
);
end entity controller_entity;

architecture controller_v1 of controller_entity is
signal cars_entered : std_logic_vector(0 to entryCount-1);

component entry is
    port(
        clk       : in  std_logic;
        ....
        car_passed: out std_logic  --Output to higher level
    );
end component;

begin   
    CREATE_ENTRANCES: for i in 0 to entryCount-1 generate
                entryi : entry port map(clk => clk,
                        ....
                car_passed => entry_car_entered(i) -- This line causes the problem.                                             

                        end generate CREATE_ENTRANCES;

    .....

);
end architecture controller_v1;

我想如果我改用VHDL 2008进行编译，可以解决此问题，但我想坚持与1993年有关。对此问题的任何建议将不胜感激。

I think I can fix this if I switch to compiling with VHDL 2008 but I'm trying to stick with 1993. Any advice on this issue would be deeply appreciated.

推荐答案

VHDL-2008允许在内部读取端口 out 模式，但以前的VHDL版本没有，因此基于错误消息无法读取输出状态，以及您对通过使用VHDL-2008解决问题的评论，

VHDL-2008 allows internal use in read of a port in out mode, but previous VHDL versions does not, so based on the error message 'Cannot read output status', and your comment about fixing the problem through use of VHDL-2008, it sounds like this is the problem.

但是，错误消息实际上可能是无法读取输出状态，其中状态是对输出的引用在未公开代码的其他位置命名为状态。您可能需要在所有代码中搜索状态，以查看是否引用了模式为 out 的状态端口进行读取。

However, the error message may actually be 'Cannot read output "status"', where "status" is a reference to an output named "status" elsewhere in undisclosed code. You may want to search for "status" in all code, to see if a "status" port with mode out is referenced for read.

如果是这样，如果内部信号由组件驱动，则该问题可以在VHDL-2002中解决，然后内部信号将输出港口。然后可以在内部读取此内部信号。

If so, the problem can be fixed in VHDL-2002 if an internal signal is driven by the component, and the internal signal then drives the out port. This internal signal may then be read internally.

这篇关于VHDL：无法读取输出状态的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！