如何在VHDL中将信号延迟几个周期 [英] how to delay a signal for several cycles in vhdl

问题描述

如何在VHDL中将信号延迟给定的周期数？
循环数是通用的。

How to delay signal for a given number of cycles in VHDL? Number of cycles is given as a generic.

可以用其他任何方式代替

Any other options instead of

process(CLK) is
begin
  if rising_edge(CLK) then
    a_q <= a;
    a_q_q <= a_q;
    a_q_q_q <= a_q_q;
    -- etc
  end if;
end process;

？

推荐答案

创建一个信号类型合适的1-d数组（我们称其为 a_store ），数组的长度与周期数有关。这可能意味着您必须为数组创建一个新类型，除非已经可以使用矢量类型： std_logic_vector 或 integer_vector （后者仅在VHDL-2008中为标准）。

Create an 1-d array (let's call it a_store) of the appropriate type of signal with the length of the array related to the number of cycles. This may mean you have to create a new type for the array unless there's already a vector type you can use: eg. std_logic_vector or integer_vector (the latter is standard only in VHDL-2008).

然后沿着每个刻度移动数组：

Then shuffle the array along each tick:

if rising_edge(clk) then
  a_store <= a_store(store'high-1 downto 0) & a;
  a_out <= a_store(a_store'high);
end if;

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