VHDL中信号的边缘检测 [英] Edge detection of signal in VHDL
问题描述
我是 VHDL 新手，我有一个按钮，我想在按下它时检测它的信号，这意味着我想在按下时检测信号按钮的上升沿?
我做了研究，我发现的所有内容都是关于检测时钟的上升沿.
我遇到的问题是，当按下按钮时，按钮的信号变为 1 并保持在 1 直到另一个甚至发生，所以当按钮的信号升高时我更感兴趣?
你的地道英语问题:
<块引用>我是 VHDL 新手，有一个按钮，我想将其检测为按下时上升沿.
我做了一些研究，我发现的所有内容都是关于检测时钟的上升沿.
当按下按钮时，按钮的信号变为'1' 并保持在 '1' 直到另一个事件发生.
如何检测按钮上升沿事件?
这不是一个 VHDL 问题，而是一个数字设计问题.VHDL 可用于在 VHDL 中实现解决方案.
请参阅 sonicwave 对问题的回答
请注意，Maxim 网页文章提到薄膜开关在新的和随时间退化的情况下可以无弹跳，并且弹跳特性不可重复.
一些 FPGA 供应商在按钮之间提供施密特触发器缓冲区，并声称薄膜瞬时开关随后会去抖动".Maxim 网络文章声称薄膜开关在其使用寿命内可能无法保持清洁.这些和其他类型的瞬时开关可能需要去抖动.
去抖动
当 FPGA 板不提供去抖动功能时，想法是以数字方式过滤掉所有这些反弹并生成一个显示按钮已被按下的事件.这需要一个时钟.
首先将按钮信号输入您的时钟域
这需要亚稳态滤波，这是通过最小化两个连续触发器之间的延迟来实现的，当第一个触发器看到建立或保持时间违规时，最大限度地提高对第一个触发器的亚稳态区域内发生的事件的免疫力.
第一个触发器的输入是按钮信号，第二个触发器的输入是第一个触发器的输出.
第二个触发器的输出在时钟域中，当不超过表示由两个触发器之间的路由延迟加上触发器的亚稳态恢复时间组成的时钟速率时，无亚稳态.
触发器的亚稳态恢复时间通常用 FPGA 中的最大时钟频率周期表示.
过滤掉反弹
当按钮无效时，将经过亚稳态过滤的按钮信号馈送到计数器作为复位.当您松开按钮时，计数器会被清零.
计数器的大小取决于时钟频率和开关弹跳的长度，可能需要几十毫秒.
终端计数表示有效的按钮事件，也用于停止计数器.(终端计数 FALSE 是计数器的使能).
计数器停止提供单个按钮事件.
另请注意，当按钮输入经过亚稳态过滤时，它充当同步复位.
边缘检测
边缘检测是用一个触发器完成的，终端计数信号作为输入和一个双输入门，门的类型和输入的极性可用于选择事件的哪个边缘(可能两者都使用 XOR门)你检测到.一个输入来自触发器的门，另一个输入来自计数器的终端计数.
如果您认为 FPGA 电路板设计能够充分提供去抖动功能，您可以在不使用去抖动计数器的情况下结合亚稳态过滤和边缘检测.
Maxim 的应用笔记
如果您拥有商用生产的 FPGA 板，您就不必担心超出数字信号电平的电压瞬变，Maxim 的文章正在向电路板设计人员宣传其保护装置.
该网络文章提供了有关开关弹跳和弹跳波形的权威参考.
FPGA 主板供应商
一些 FPGA 板供应商提供去抖动电路参考设计代码.他们会这样做，因为计数器大小取决于参考时钟速率，并且可能使用的时钟由 DPLL 派生.
I am new on VHDL, I have a push button which I want to detect the it signal when it is pushed, meaning i want to detect the raising edge of the signal push button when it is pressed?
I did research and all what I found was about the detecting the raising edge of a clk.
the problem that I have is that when the push button is pressed the the signal for the push button goes to 1 and stay at 1 until until another even happen so I am interested more when the signal of the push button raise?
Your question in idiomatic English:
I am new to VHDL and have a push button that I want to detect as a rising edge when pressed.
I did some research and all what I found was about the detecting the rising edge of a clock.
When the push button is pressed the signal for the push button goes to '1' and stay at '1' until until another event occurs.
How do I detect the push button rising edge event?
This isn't so much of a VHDL question as it is a digital design question. VHDL comes into play for implementing a solution in VHDL.
See sonicwave's answer to the question VHDL - Incrementing Register Value on Push Button Event which provides an edge detector.
However switch bounce can occur for tens of milliseconds (Maxim web article on switch bounce), potentially generating multiple events, is switch dependent and corrective action also depends on sampling clock rate.
Notice the Maxim web page article mentions membrane switches can be bounce free when new and degrade over time and bounce characteristics are not repeatable.
Some FPGA vendors provide a Schmidt trigger buffer between buttons and claim membrane momentary switches are then 'debounced'. The Maxim web article claims membrane switches may not remain clean over their useful lifetime. These and other types of momentary switches can require debouncing.
debouncing
When debouncing is not provided by the FPGA board the idea is to filter out all these bounces digitally and generate a single event showing the button has been depressed. This requires a clock.
first get the button signal into your clock domain
This requires metastability filtering, which is accomplished by minimizing the delay between two successive flip flops to maximize immunity to events occurring within the metastability region of the first flip flop when the first flip flop sees a setup or hold time violation.
The input to the first flip flop is the button signal, the input to the second flip flop is the output of first flip flop.
The output of the second flip flop is in the clock domain, metastability free when not exceeding the a clock rate representing period comprised of the routing delay between the two flip flops plus the metastability recovery time of the flip flop.
The metastability recovery time of the flip flop is usually represented by the maximum clock rate period in an FPGA.
filtering out bounces
Feed the metastability filtered button signal to a counter as a reset when the button is invalid. When you release the button the counter is cleared.
The size of the counter depends on the clock rate and length of switch bounce, you can require tens of milliseconds.
A terminal count signifies a valid button event and also is used to stop the counter. (Terminal count FALSE is an enable for the counter).
The counter is stopped to provide a single button event.
Also note that when the button input is metastability filtered it acts as a synchronous reset.
Edge detection
Edge detection is done with a flip flop with the terminal count signal as an input and a two input gate, the type of gate and polarity of it's inputs can be used to select which edge of the event (potentially both with an XOR gate) you detect. One input to the gate from the flip flop, the other the terminal count from the counter.
If you've deemed debounce is provided adequately by the FPGA board design you can combine metastability filtering and edge detection without using a debounce counter.
Maxim's application note
If you have a commercially produced FPGA board you shouldn't have to worry about voltage transients outside digital signalling levels, the Maxim article is promoting their protective devices to board designers.
The web article provides an authoritative reference on switch bounce and the bounce waveforms.
FPGA board vendors
Some FPGA board vendors provide debounce circuit reference design code. They'll do this because the counter size is dependent on the reference clock rate, and potentially the clock used is derived by a DPLL.
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