在ncvhdl中获取vhdl设计的内部信号(替代modelsim的信号间谍) [英] Get internal signals of vhdl design in ncvhdl (alternative to modelsim's signal spy)

问题描述

在ModelSim中，您可以使用类似的

在模型中我们可以使用 init_signal_spy("../.../sig"，mysignal);

获得深层次的信号. Cadence的NCVhdl是否有办法获得此类信号?

应将其标记为"SimVision"，这是该工具的名称，但该标记似乎不存在.

解决方案

如果Cadence工具支持VHDL-2008，则可以通过外部名称访问设计其他级别的信号，共享变量或常量.

直接用法如下.

A <= <<signal .tb_top.u_comp1.my_sig : std_logic_vector >>; 

请注意，必须在引用之前对对象进行详细说明.由于VHDL设计是按实例化顺序进行详细说明的，因此以后的设计可以参考以前的设计.

使用别名创建本地简称:

alias u1_my_sig is <<signal u1.my_sig : std_logic_vector >>; 

路径始于:

• ." =路径从最高级别开始:.tb_top.my_sig"
• "u1" =路径从当前级别开始:"u1.my_sig"
• "^" =路径从当前位置开始:"^ u2.my_sig"

In ModelSim you can use something like

in modelsim we can use init_signal_spy("../.../sig", mysignal);

to get deep hierarchy signals. Is there a way to get such signals with Cadence's NCVhdl?

This should be flagged "SimVision", which is the name the tool, but that flag does not seem to exist.

解决方案

If Cadence tools support VHDL-2008, you can access signals, shared variables, or constants in other levels of your design via external names.

Direct usage is as follows.

A <= <<signal .tb_top.u_comp1.my_sig : std_logic_vector >>; 

Note that the object must be elaborated before the reference. Since VHDL designs are elaborated in order of instantiation later designs may reference into earlier ones.

Use an alias to create a local short hand name:

alias u1_my_sig is <<signal u1.my_sig : std_logic_vector >>; 

Path starts with:

• "." = path starts at top level: ".tb_top.my_sig"
• "u1" = path starts from current level: "u1.my_sig"
• "^" = path starts from level above current: "^u2.my_sig"

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