VHDL:零扩展固定信号值 [英] VHDL: Zero-Extend a fixed signal value

问题描述

如何对固定信号值进行零扩展?

How do you zero-extend a fixed signal value?

我有以下信号:

signal shamt: std_logic_vector(4 downto 0);

在我将它分配给另一个大小为 31 到 0 的变量之前，我必须将 shamt 扩展为零.我有以下代码，但我不确定它是否正确.

Before I assign it to another variable that is of size 31 downto 0 I have to zero extend shamt. I have the following code but I am unsure if it is correct.

muxSOut <= conv_std_logic_vector(unsigned(shamt),32) when (muxSSel = '0') else A;

我对 conv_std_logic_vector(unsigned(shamt), 32) 部分持怀疑态度.

I'm skeptical about the part conv_std_logic_vector(unsigned(shamt), 32).

这会将 5 位大小的 shamt 扩展到 32 位吗?因此，如果 shamt 是 11011，那么它只会是 27 个 0，然后是 11011?如果不是，零扩展错误的正确方法是什么?

Will this extend shamt, which is of 5 bit size to 32 bit? So if shamt was 11011 it would just be 27 0s and then 11011? If not, what is the correct way to zero extend shamt?

推荐答案

一种(标准)方法是使用 ieee.numeric_std 和 resize().例如:

One (standard) method is to use ieee.numeric_std and resize(). e.g.:

muxSOut <= std_logic_vector(resize(unsigned(shamt), 32)) ...

这样做的一个好处是您可以将 32 替换为 muxSOut'length，然后您的代码就会变得更加灵活.

One advantage of this is that you can replace 32 with muxSOut'length, and then your code becomes a bit more flexible.

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