VHDL 变量 Vs.信号 [英] VHDL Variable Vs. Signal

问题描述

我一直在阅读有关 VHDL 编程的文本(前面没有，所以无法给出标题).我一直很难从文本中理解的一个问题是何时使用变量与信号.我想我对何时使用信号(即内部信号)有清晰的了解，但对于变量却没有那么多.

I have been reading a text (Don't have it in front so can't give the title) about VHDL programming. One problem I've been having a hard time understanding from the text is when to use a variable vs a signal. I think I have a clear understanding of when to use a signal (internal signal that is) but not so much for a variable.

我确实注意到文本通常在定义进程之前声明和初始化信号，而变量是在进程内部声明的(我猜从来没有初始化......).

I did notice that the text generally declares and initializes signals before defining a process whereas a variable is declared (and I guess never initialized..) inside of a process.

无论如何，通过定义或示例来澄清这一点都很棒！

Anyway to clear that up, either by definition or by example would be great!

推荐答案

变量用于创建序列化代码，与普通并行代码不同.(序列化意味着命令按顺序执行，一个接一个而不是一起执行).一个变量只能存在于一个进程中，值的赋值不是并行的.例如，考虑以下代码:

Variables are used when you want to create serialized code, unlike the normal parallel code. (Serialized means that the commands are executed in their order, one after the other instead of together). A variable can exist only inside a process, and the assignment of values is not parallel. For example, consider the following code:

signal a,b : std_logic_vector(0 to 4);

process (CLK)
    begin
        if (rising_edge(clk)) then
            a <= '11111';
            b <= a;
        end if;
end process;

将在进程运行之前将a的值放入b，而不是'11111'.另一方面，代码:

will put into b the value of a before the process ran, and not '11111'. On the other hand, the code:

signal a,b : std_logic_vector(0 to 4);

process (CLK)
    variable var : std_logic_vector(0 to 4);
    begin 
        if (rising_edge(clk)) then
            var := '11111';
            a <= var;
            b <= var;
        end if;
end process;

会将值 '11111' 放入 a 和 b.

will put the value '11111' into both a and b.

坦率地说，根据我的经验，大多数时候你不需要使用变量，我唯一使用它的地方是在一个循环中，我需要检查多个信号中的任何一个是否为 1:

Frankly, in my experience, most of the time you don't need to use variables, the only place I used it was in a loop where I needed to check if any of a number of signals is 1:

type    BitArray        is array (natural range <>) of std_logic;

--...

entity CAU_FARM is
    port
        (
            --   IN   --
              REQUEST         : in BitArray(0 to (FLOW_num -1));
              --..
        );
end CAU_FARM;
--...

farm_proc: process(CLK_FARM, RESET)
    variable request_was_made_var : std_logic;
    begin
    if RESET = C_INIT then 
       -- ...

    elsif rising_edge(CLK_FARM) then

            -- read state machine --
        case read_state is
            when        st_read_idle =>

                request_was_made_var := '0';
                for i in 0 to (FLOW_num -1) loop
                    if (REQUEST(i) = '1') then
                        request_was_made_var := '1';
                    end if;
                end loop;
                if (request_was_made_var = '1') and (chosen_cau_read_sig /= 8) then
                    read_state <= st_read_stage_1;
                    for i in 0 to (FLOW_num -1) loop
                        if (i = choice_out_sig) then
                            ACKNOWLEDGE(i) <= '1';
                        end if;
                    end loop;
                else
                    read_state <= st_read_idle;
                end if;
            ------------------------
            when        st_read_stage_1 =>
            --...

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