如何在 VHDL 测试平台中轻松分组和驱动信号 [英] How to easily group and drive signals in VHDL testbench

问题描述

假设我有 3 个控制信号 A、B 和 C.

Let's say I have 3 control signals A, B and C.

在测试平台中，VHDL 中有一个函数可以将其分组并快速迭代所有案例(例如，使它们能够使用 for 循环进行迭代)，而不是写出 8 个案例.

In the testbench is there a function in VHDL to group this and iterate all cases quickly (to enable them to be iterated with a for loop for example) rather than write out 8 cases.

伪代码示例:

for i in range 0 to 7
 grouped_signals <=std_logic_vector(to_unsigned(i,3)

推荐答案

它可以是一个信号赋值，其中目标是一个聚合:

It can be a signal assignment where the target is an aggregate:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity agg_assign is
end entity;

architecture foo of agg_assign is
    signal A, B, C: std_logic;
begin
    process
    begin
        wait for 10 ns;
        for i in 0 to 7 loop
            (A, B, C) <= std_logic_vector(to_unsigned(i, 3));
            wait for 10 ns;
        end loop;
        wait;
    end process;
end architecture;

这会产生:

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